| Message ID | 20241231194207.2772750-2-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | iio: adc: meson: add MPLL clock workaround for GXLX | expand |
On Tue, Dec 31, 2024 at 08:42:06PM +0100, Martin Blumenstingl wrote: > Add a compatible string for the GXLX SoC. It's very similar to GXL but > has three additional bits in MESON_SAR_ADC_REG12 for the three MPLL > clocks. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > .../devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml | 1 + > 1 file changed, 1 insertion(+) Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml index b0962a4583ac..bb9825e7346d 100644 --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml @@ -23,6 +23,7 @@ properties: - amlogic,meson8m2-saradc - amlogic,meson-gxbb-saradc - amlogic,meson-gxl-saradc + - amlogic,meson-gxlx-saradc - amlogic,meson-gxm-saradc - amlogic,meson-axg-saradc - amlogic,meson-g12a-saradc
Add a compatible string for the GXLX SoC. It's very similar to GXL but has three additional bits in MESON_SAR_ADC_REG12 for the three MPLL clocks. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- .../devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml | 1 + 1 file changed, 1 insertion(+)