From patchwork Fri Jan 3 07:31:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 13925284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 090E1E77188 for ; Fri, 3 Jan 2025 07:34:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=zlQ1rc3p+TAIe+/t15kga73c3kmATfUyNhYy/EYoGLM=; b=dyMfp1FeCSu3MIx6Fs3A2g7Psy 7LkzQjf0uDQEIw1BG7IilGtTG60Wfs45OOgJ7EqxStC4x+Bd8prDnzxM6tAeNuCSkcfS2sIBYZp21 RJbk3Hhc6HlhydumopRgHMqCondG8EJvWWzqtxDQv8X0yxTBQ+iEkAnx3rGzuhJE7H//D8iJBepJb xos25lftxWTUxTiLmI5yYdsZcJxAK7EUhsAThsC+Ir+Dk5qrXco6SEPNFd7hfd74vz3C/1RmPrPgI hCKV9otRYAkusJfn4oStc2nN54pNjgY12KdCcuYUiUcVKljW1lcHfs907+cjquiBsJCwaOCXSzQ2g 0lOgb0kA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tTcCN-0000000CM5L-3fdW; Fri, 03 Jan 2025 07:34:23 +0000 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tTcA2-0000000CLX9-0Fsd for linux-arm-kernel@lists.infradead.org; Fri, 03 Jan 2025 07:31:59 +0000 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5037Niqk022926; Fri, 3 Jan 2025 07:31:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zlQ1rc3p+TAIe+/t15kga73c3kmATfUyNhYy/EYoGLM=; b=oIa5z70gTYNqpXWi gYjstU6NbpaNA7zYYgJiOptAC5Ns2959cRRxobg1EqmHTr0CWrM0QtNlGmTMOFm5 y7/pOPIcrWsFjtaXPKeBX79L9LesRO6DdVR2+n9PQAMECyB39mNx3ONAvGuKblnz yjFBETGYPNgobEru8T38w0vZxl0HNAWcFCwBMUGBcVRD0O0WI2JisjD/hmwIeD2/ XRfyKKmirbtJAtoRogsDBhcfqOEKSUect8ZxzOKG38ZOxR1shLGM6nAjFuz4ZmCz L3zrKk5k+wAaocG2PD/uwQVTkgAW9KbWX0Vah1bq6Xs5jwIvJh4ru42dTkv5RUEi CZpDFw== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43xbfe80ey-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 03 Jan 2025 07:31:50 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5037VnQW018168 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 3 Jan 2025 07:31:49 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 2 Jan 2025 23:31:44 -0800 From: Luo Jie Date: Fri, 3 Jan 2025 15:31:34 +0800 Subject: [PATCH v8 1/5] dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC MIME-Version: 1.0 Message-ID: <20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com> References: <20250103-qcom_ipq_cmnpll-v8-0-c89fb4d4849d@quicinc.com> In-Reply-To: <20250103-qcom_ipq_cmnpll-v8-0-c89fb4d4849d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1735889498; l=4395; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=J4AZvvPrP13qr+YOE501Z8KHhcEYuflT6CDYfcz0jS0=; b=OfHZMss8aTCC9/5A3wzjBx5K9uB3FPybtBz4qCFN/WOA3ERx7ptHDf5QMSypH277of7BRujJZ kCj6Y0OQxrrCoR0toOOBFB+qVYtNXVRvn9+ti1LKG0msbcoXgtA9jIN X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=P81jeEL23FcOkZtXZXeDDiPwIwgAHVZFASJV12w3U6w= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xZhoFXuJfzSVtwxklzWov4r5Y6gz6XNC X-Proofpoint-ORIG-GUID: xZhoFXuJfzSVtwxklzWov4r5Y6gz6XNC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 adultscore=0 suspectscore=0 phishscore=0 spamscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501030064 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250102_233158_223417_2A6CADE2 X-CRM114-Status: GOOD ( 15.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CMN PLL controller provides clocks to networking hardware blocks and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, and produces output clocks at fixed rates. These output rates are predetermined, and are unrelated to the input clock rate. The primary purpose of CMN PLL is to supply clocks to the networking hardware such as PPE (packet process engine), PCS and the externally connected switch or PHY device. The CMN PLL block also outputs fixed rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep clock supplied to GCC. Signed-off-by: Luo Jie Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 77 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 22 +++++++ 2 files changed, 99 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml new file mode 100644 index 000000000000..f869b3739be8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm CMN PLL Clock Controller on IPQ SoC + +maintainers: + - Bjorn Andersson + - Luo Jie + +description: + The CMN (or common) PLL clock controller expects a reference + input clock. This reference clock is from the on-board Wi-Fi. + The CMN PLL supplies a number of fixed rate output clocks to + the devices providing networking functions and to GCC. These + networking hardware include PPE (packet process engine), PCS + and the externally connected switch or PHY devices. The CMN + PLL block also outputs fixed rate clocks to GCC. The PLL's + primary function is to enable fixed rate output clocks for + networking hardware functions used with the IPQ SoC. + +properties: + compatible: + enum: + - qcom,ipq9574-cmn-pll + + reg: + maxItems: 1 + + clocks: + items: + - description: The reference clock. The supported clock rates include + 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ. + - description: The AHB clock + - description: The SYS clock + description: + The reference clock is the source clock of CMN PLL, which is from the + Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL + clock registers. + + clock-names: + items: + - const: ref + - const: ahb + - const: sys + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq9574-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h new file mode 100644 index 000000000000..936e92b3b62c --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H + +/* CMN PLL core clock. */ +#define CMN_PLL_CLK 0 + +/* The output clocks from CMN PLL of IPQ9574. */ +#define XO_24MHZ_CLK 1 +#define SLEEP_32KHZ_CLK 2 +#define PCS_31P25MHZ_CLK 3 +#define NSS_1200MHZ_CLK 4 +#define PPE_353MHZ_CLK 5 +#define ETH0_50MHZ_CLK 6 +#define ETH1_50MHZ_CLK 7 +#define ETH2_50MHZ_CLK 8 +#define ETH_25MHZ_CLK 9 +#endif