| Message ID | 20250109102627.1366753-2-romain.naour@smile.fr (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v4,1/2] dt-bindings: mfd: syscon: Add ti,j721e-acspcie-proxy-ctrl compatible | expand |
On Thu, Jan 09, 2025 at 11:26:27AM +0100, Romain Naour wrote: Hello Romain, > From: Romain Naour <romain.naour@skf.com> > > Unlike the SK-TDA4VM (k3-j721e-sk) board, there is no clock generator > (CDCI6214RGET) on the BeagleBone AI-64 (k3-j721e-beagleboneai64) to > provide PCIe refclk signal to PCIe Endponts. So the ACSPCIE module must > provide refclk through PCIe_REFCLK pins. > > Use the new "ti,syscon-acspcie-proxy-ctrl" property to enable ACSPCIE > module's PAD IO Buffers. > > Cc: Siddharth Vadapalli <s-vadapalli@ti.com> > Signed-off-by: Romain Naour <romain.naour@skf.com> > --- > With this patch, we can remove "HACK: Sierra: Drive clock out" patch > applied on vendor kernel for BeagleBone AI-64: > https://openbeagle.org/beagleboard/linux/-/commit/ad65d7ef675966cdbc5d75f2bd545fad1914ba9b [trimmed] > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > index af3d730154ac..32a232a90100 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > @@ -5,6 +5,7 @@ > * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ > */ > #include <dt-bindings/phy/phy.h> > +#include <dt-bindings/phy/phy-cadence.h> > #include <dt-bindings/phy/phy-ti.h> > #include <dt-bindings/mux/mux.h> > > @@ -82,6 +83,11 @@ ehrpwm_tbclk: clock-controller@4140 { > reg = <0x4140 0x18>; > #clock-cells = <1>; > }; > + > + acspcie0_proxy_ctrl: syscon@18090 { > + compatible = "ti,j721e-acspcie-proxy-ctrl", "syscon"; > + reg = <0x18090 0x4>; 0x_0011_8090 is probably *not* the "PROXY" register i.e. it could be locked with the help of "CTRLMMR_LOCK0_KICK0" and "CTRLMMR_LOCK0_KICK1" registers, in which case the CTRL_MMR region needs to be unlocked to write to that register. On J784S4, that happens to be true, which is why the proxy register 0x_0011_a090 was used at [0]. Please test with 0x_0011_a090 which is the "PROXY" register on J721E as well, i.e. it can be written to unconditionally. [0]: https://lore.kernel.org/r/20240930111505.3101047-1-s-vadapalli@ti.com/ [trimmed] Regards, Siddharth.
Hello Siddharth, All, Le 09/01/2025 à 12:49, Siddharth Vadapalli a écrit : > On Thu, Jan 09, 2025 at 11:26:27AM +0100, Romain Naour wrote: > > Hello Romain, > >> From: Romain Naour <romain.naour@skf.com> >> >> Unlike the SK-TDA4VM (k3-j721e-sk) board, there is no clock generator >> (CDCI6214RGET) on the BeagleBone AI-64 (k3-j721e-beagleboneai64) to >> provide PCIe refclk signal to PCIe Endponts. So the ACSPCIE module must >> provide refclk through PCIe_REFCLK pins. >> >> Use the new "ti,syscon-acspcie-proxy-ctrl" property to enable ACSPCIE >> module's PAD IO Buffers. >> >> Cc: Siddharth Vadapalli <s-vadapalli@ti.com> >> Signed-off-by: Romain Naour <romain.naour@skf.com> >> --- >> With this patch, we can remove "HACK: Sierra: Drive clock out" patch >> applied on vendor kernel for BeagleBone AI-64: >> https://openbeagle.org/beagleboard/linux/-/commit/ad65d7ef675966cdbc5d75f2bd545fad1914ba9b > > [trimmed] > >> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >> index af3d730154ac..32a232a90100 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >> @@ -5,6 +5,7 @@ >> * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ >> */ >> #include <dt-bindings/phy/phy.h> >> +#include <dt-bindings/phy/phy-cadence.h> >> #include <dt-bindings/phy/phy-ti.h> >> #include <dt-bindings/mux/mux.h> >> >> @@ -82,6 +83,11 @@ ehrpwm_tbclk: clock-controller@4140 { >> reg = <0x4140 0x18>; >> #clock-cells = <1>; >> }; >> + >> + acspcie0_proxy_ctrl: syscon@18090 { >> + compatible = "ti,j721e-acspcie-proxy-ctrl", "syscon"; >> + reg = <0x18090 0x4>; > > 0x_0011_8090 is probably *not* the "PROXY" register i.e. it could be > locked with the help of "CTRLMMR_LOCK0_KICK0" and "CTRLMMR_LOCK0_KICK1" > registers, in which case the CTRL_MMR region needs to be unlocked to write > to that register. On J784S4, that happens to be true, which is why the > proxy register 0x_0011_a090 was used at [0]. Please test with 0x_0011_a090 > which is the "PROXY" register on J721E as well, i.e. it can be written to > unconditionally. > > [0]: > https://lore.kernel.org/r/20240930111505.3101047-1-s-vadapalli@ti.com/ Thanks for the review! Actually the Proxy0 vs Proxy1 choice is not really clear for me. We have two proxy to reach the same register: CTRLMMR_ACSPCIE0_CTRL Register (Proxy0 Offset = 18090h; Proxy1 Offset = 1A090h) From my testing both addresses works (maybe since my SoC is a general purpose one). When and why Proxy1 must be used? Otherwise I'm fine to use 0x_0011_a090. Best regards, Romain > > [trimmed] > > Regards, > Siddharth.
On 1/9/25 4:26 AM, Romain Naour wrote: > From: Romain Naour <romain.naour@skf.com> > > Unlike the SK-TDA4VM (k3-j721e-sk) board, there is no clock generator > (CDCI6214RGET) on the BeagleBone AI-64 (k3-j721e-beagleboneai64) to > provide PCIe refclk signal to PCIe Endponts. So the ACSPCIE module must > provide refclk through PCIe_REFCLK pins. > > Use the new "ti,syscon-acspcie-proxy-ctrl" property to enable ACSPCIE > module's PAD IO Buffers. > > Cc: Siddharth Vadapalli <s-vadapalli@ti.com> > Signed-off-by: Romain Naour <romain.naour@skf.com> > --- > With this patch, we can remove "HACK: Sierra: Drive clock out" patch > applied on vendor kernel for BeagleBone AI-64: > https://openbeagle.org/beagleboard/linux/-/commit/ad65d7ef675966cdbc5d75f2bd545fad1914ba9b > > v4: no change > > v3: > - update "acspcie0_proxy_ctrl" compatible to "ti,j721e-acspcie-proxy-ctrl" > since this property is specific to j721e variant. > > v2: > - use generic style comments > - use "syscon" as generic node name for "acspcie0_proxy_ctrl" node > - Keep the compatible "ti,j784s4-acspcie-proxy-ctrl" since the > ACSPCIE buffer and its functionality is the same across all K3 SoCs. > (Siddharth Vadapalli) > > "The compatible "ti,j784s4-acspcie-pcie-ctrl" should be reused for > J721E and all other K3 SoCs. > For example, see: > https://lore.kernel.org/r/20240402105708.4114146-1-s-vadapalli@ti.com/ > which introduced "ti,am62p-cpsw-mac-efuse" compatible. > > The same compatible is reused across all K3 SoCs: > https://lore.kernel.org/r/20240628151518.40100-1-afd@ti.com/ " > --- > arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 5 +++++ > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 10 ++++++++-- > 2 files changed, 13 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts > index fb899c99753e..741ad2ba6fdb 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts > +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts > @@ -859,6 +859,11 @@ &pcie1_rc { > num-lanes = <2>; > max-link-speed = <3>; > reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; > + /* > + * There is no on-board or external reference clock generators, > + * use refclk from the ACSPCIE module's PAD IO Buffers. > + */ > + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; > }; > > &ufs_wrapper { > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > index af3d730154ac..32a232a90100 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > @@ -5,6 +5,7 @@ > * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ > */ > #include <dt-bindings/phy/phy.h> > +#include <dt-bindings/phy/phy-cadence.h> > #include <dt-bindings/phy/phy-ti.h> > #include <dt-bindings/mux/mux.h> > > @@ -82,6 +83,11 @@ ehrpwm_tbclk: clock-controller@4140 { > reg = <0x4140 0x18>; > #clock-cells = <1>; > }; > + > + acspcie0_proxy_ctrl: syscon@18090 { > + compatible = "ti,j721e-acspcie-proxy-ctrl", "syscon"; > + reg = <0x18090 0x4>; > + }; You'll still need to add to the J721e system controller binding or this will throw a DT check warning, something like this: diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml index 378e9cc5fac2a..3323f3bc976e0 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml @@ -68,6 +68,12 @@ patternProperties: description: The node corresponding to SoC chip identification. + "^acspcie-ctrl@[0-9a-f]+$": + type: object + $ref: /schemas/mfd/syscon.yaml# + description: + This is the ASPCIe control region. + required: - compatible - reg > }; > > main_ehrpwm0: pwm@3000000 { > @@ -979,8 +985,8 @@ pcie1_rc: pcie@2910000 { > max-link-speed = <3>; > num-lanes = <2>; > power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; > - clocks = <&k3_clks 240 1>; > - clock-names = "fck"; > + clocks = <&k3_clks 240 1>, <&serdes1 CDNS_SIERRA_DERIVED_REFCLK>; > + clock-names = "fck", "pcie_refclk"; > #address-cells = <3>; > #size-cells = <2>; > bus-range = <0x0 0xff>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index fb899c99753e..741ad2ba6fdb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -859,6 +859,11 @@ &pcie1_rc { num-lanes = <2>; max-link-speed = <3>; reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; + /* + * There is no on-board or external reference clock generators, + * use refclk from the ACSPCIE module's PAD IO Buffers. + */ + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; }; &ufs_wrapper { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index af3d730154ac..32a232a90100 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy.h> +#include <dt-bindings/phy/phy-cadence.h> #include <dt-bindings/phy/phy-ti.h> #include <dt-bindings/mux/mux.h> @@ -82,6 +83,11 @@ ehrpwm_tbclk: clock-controller@4140 { reg = <0x4140 0x18>; #clock-cells = <1>; }; + + acspcie0_proxy_ctrl: syscon@18090 { + compatible = "ti,j721e-acspcie-proxy-ctrl", "syscon"; + reg = <0x18090 0x4>; + }; }; main_ehrpwm0: pwm@3000000 { @@ -979,8 +985,8 @@ pcie1_rc: pcie@2910000 { max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 1>; - clock-names = "fck"; + clocks = <&k3_clks 240 1>, <&serdes1 CDNS_SIERRA_DERIVED_REFCLK>; + clock-names = "fck", "pcie_refclk"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>;