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Fri, 10 Jan 2025 10:20:05 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE4.st.com (10.75.129.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Fri, 10 Jan 2025 10:20:05 +0100 Received: from localhost (10.252.28.64) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Fri, 10 Jan 2025 10:20:04 +0100 From: Fabrice Gasnier To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 7/8] arm64: dts: st: add timer pins for stm32mp257f-ev1 Date: Fri, 10 Jan 2025 10:19:21 +0100 Message-ID: <20250110091922.980627-8-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250110091922.980627-1-fabrice.gasnier@foss.st.com> References: <20250110091922.980627-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.28.64] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250110_012220_235210_ACF2A986 X-CRM114-Status: GOOD ( 11.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add timer pins available on stm32mp257f-ev1, configured for PWM: - timer3 CH2 is available on mikroBUS connector - timer8 CH1, timer8 CH4, timer10 CH1 and timer12 CH2 are available on EXPANSION connector Arbitrary define all these pins to be used as PWM (output) channels, except for timer10 CH1, to be used as counter input. Signed-off-by: Fabrice Gasnier --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 8fdd5f020425..bb9dc82d3dd5 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -82,6 +82,53 @@ pins { }; }; + pwm3_pins_a: pwm3-0 { + pins { + pinmux = ; /* TIM3_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_a: pwm3-sleep-0 { + pins { + pinmux = ; /* TIM3_CH2 */ + }; + }; + + pwm8_pins_a: pwm8-0 { + pins { + pinmux = , /* TIM8_CH1 */ + ; /* TIM8_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_a: pwm8-sleep-0 { + pins { + pinmux = , /* TIM8_CH1 */ + ; /* TIM8_CH4 */ + }; + }; + + pwm12_pins_a: pwm12-0 { + pins { + pinmux = ; /* TIM12_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm12_sleep_pins_a: pwm12-sleep-0 { + pins { + pinmux = ; /* TIM12_CH2 */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = , /* SDMMC1_D0 */ @@ -158,6 +205,20 @@ pins1 { }; }; + tim10_counter_pins_a: tim10-counter-0 { + pins { + pinmux = ; /* TIM10_CH1 */ + bias-disable; + }; + }; + + tim10_counter_sleep_pins_a: tim10-counter-sleep-0 { + pins { + pinmux = ; /* TIM10_CH1 */ + bias-disable; + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = ; /* USART2_TX */