| Message ID | 20250110123835.2719824-5-paul-pl.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
On Fri, 10 Jan 2025 20:33:59 +0800, paul-pl.chen wrote: > From: "Paul-pl.Chen" <paul-pl.chen@mediatek.com> > > Add mediatek,exdma.yaml to support EXDMA for MT8196. > > Signed-off-by: Paul-pl.Chen <paul-pl.chen@mediatek.com> > --- > The header used in examples: > #include <dt-bindings/clock/mt8196-clk.h> > #include <dt-bindings/power/mt8196-power.h> > are not upstreamed yet. > It will be sent by related owner soon. > --- > .../display/mediatek/mediatek,exdma.yaml | 77 +++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,exdma.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/mediatek/mediatek,exdma.example.dts:18:18: fatal error: dt-bindings/clock/mt8196-clk.h: No such file or directory 18 | #include <dt-bindings/clock/mt8196-clk.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[2]: *** [scripts/Makefile.dtbs:131: Documentation/devicetree/bindings/display/mediatek/mediatek,exdma.example.dtb] Error 1 make[2]: *** Waiting for unfinished jobs.... make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1506: dt_binding_check] Error 2 make: *** [Makefile:251: __sub-make] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250110123835.2719824-5-paul-pl.chen@mediatek.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,exdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,exdma.yaml new file mode 100644 index 000000000000..385f5549dfaa --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,exdma.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,exdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek EXDMA + +maintainers: + - Chun-Kuang Hu <chunkuang.hu@kernel.org> + - Philipp Zabel <p.zabel@pengutronix.de> + +description: + The MediaTek display overlap extended DMA engine, namely OVL_EXDMA or EXDMA, + primarily functions as a DMA engine for reading data from DRAM with various + DRAM footprints and data formats. For input sources in certain color formats + and color domains, OVL_EXDMA also includes a color transfer function + to process pixels into a consistent color domain. + +properties: + compatible: + const: mediatek,mt8196-exdma + + reg: + maxItems: 1 + + clocks: + items: + - description: EXDMA Clock + + power-domains: + maxItems: 1 + + mediatek,larb: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + items: + maxItems: 1 + description: | + A phandle to the local arbiters node in the current SoCs. + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. + + iommus: + maxItems: 1 + + '#dma-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - mediatek,larb + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8196-clk.h> + #include <dt-bindings/power/mt8196-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + disp_ovl0_exdma2: dma-controller@32850000 { + compatible = "mediatek,mt8196-exdma"; + reg = <0 0x32850000 0 0x1000>; + clocks = <&ovlsys_config_clk CLK_OVL_EXDMA2_DISP>; + power-domains = <&hfrpsys MT8196_POWER_DOMAIN_OVL0_DORMANT>; + mediatek,larb = <&smi_larb0>; + iommus = <&mm_smmu 144>; + #dma-cells = <1>; + }; + };