From patchwork Wed Jan 15 06:41:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 13939897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0259C02180 for ; Wed, 15 Jan 2025 06:46:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To: References:Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version: Subject:Date:From:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cfl57bg2TxblHHPeaG/j3oAnedbV0vgIQriu9p9SXX8=; b=CfA5I/bht9nnxMqJnNLEKt9m3M 7LjVm8Nb4oDec20ViYEbclt6hSqEiSxl+qM/uXjOKECTXZUt4gDMM4mf+iW+NLFBRXIndND940+LJ uPr7hd9YwWktrSK2fHpgu79Tw8N1VqVsHwd5KwOY5fJGZaU+SzU8UcV+epVmoGKdNORA7bW5D3ZUx N1jKMRLN1UEw2+u71MEYkFDdy93vhsUycgykQVRe1ccOMwdaUWWct7anHvIambnJFpT7rPKtaHfT4 sPoRPRtVS9JsMIEvjyS24wx9cJOWGH4N+FWpPggOz/TltXUyp3tyqo760vNujwSwl4sdxWcwyiH/L XGvb1U4g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tXxA1-0000000AqR0-3hcy; Wed, 15 Jan 2025 06:45:53 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tXx6J-0000000Apfn-2p3Q; Wed, 15 Jan 2025 06:42:05 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id E0ED45C59ED; Wed, 15 Jan 2025 06:41:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id 57976C4CEE3; Wed, 15 Jan 2025 06:42:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736923322; bh=kUfc1krOh8JPSRHIs3171DVKGYtEvs/ci1gfBYmLqSU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Uh2Ur9T45xfoQIXtUsWPsmgkCrA6TwQMay05Xktp0s8KIZmaI3pcV9Eccnty9CgZ/ MJlpICOsQamvVFB0Djb8iv9xVIi0xzbB3GKmZ2kvMl9B5vQaEanjwA3hTITRt+VijM bUBLT6u/e/vajjDVlJFDTKhCD5CojeznC7fUF9MEa+9fz8cvVzqTARU9mwxR5fketo 60YUk20rQr3Mglrg1NyOs9+qXS6Wch/nSnSVHpEy5gcfzAG1y9l0j4Dc0Nths0zp9L fJYxuAm97l4Fa6KC+La+sRTMepcHyS1hQJCMh5R/kWkuYBqlw5uk6RAV3e33Nea8BK W7WfHVtNednjw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44914C02183; Wed, 15 Jan 2025 06:42:02 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 15 Jan 2025 14:41:59 +0800 Subject: [PATCH v3 1/5] dt-bindings: pinctrl: Add support for Amlogic SoCs MIME-Version: 1.0 Message-Id: <20250115-amlogic-pinctrl-v3-1-2b8536457aba@amlogic.com> References: <20250115-amlogic-pinctrl-v3-0-2b8536457aba@amlogic.com> In-Reply-To: <20250115-amlogic-pinctrl-v3-0-2b8536457aba@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736923319; l=5559; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=LleV4eKYRjgHk06xx+Pt9rxMa6atothk5VMgpSkY4LY=; b=BvnYQcSfUQ0QaQOABEwwb10q+rATGlqBXDz6q6t/IohvWV+8YhIzDUCGBsemDYAXq8dpf/DfO 3P+bKaEOiQ1DKfInJoVKulcW+ACixqXjxPweK8N95KkDgmA7dgZGAIt X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250114_224203_809036_2BF2AA8F X-CRM114-Status: GOOD ( 12.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: xianwei.zhao@amlogic.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Xianwei Zhao Add the dt-bindings for Amlogic pin controller, and add a new dt-binding header file which document the GPIO bank names of all Amlogic subsequent SoCs. Signed-off-by: Xianwei Zhao --- .../bindings/pinctrl/amlogic,pinctrl-a4.yaml | 132 +++++++++++++++++++++ include/dt-bindings/pinctrl/amlogic,pinctrl.h | 46 +++++++ 2 files changed, 178 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml new file mode 100644 index 000000000000..bc2764549471 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/amlogic,pinctrl-a4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic pinmux controller + +maintainers: + - Xianwei Zhao + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: amlogic,pinctrl-a4 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +required: + - compatible + - "#address-cells" + - "#size-cells" + +patternProperties: + "^gpio@[0-9a-f]+$": + type: object + + properties: + reg: + minItems: 1 + items: + - description: pin config register + - description: pin mux setting register (some special pin fixed function) + - description: pin drive strength register (optionanl) + + reg-names: + minItems: 1 + items: + - const: gpio + - const: mux + - const: ds + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + maxItems: 1 + + bank-number: + description: | + bank-number are provided by the pin controller header file at: + + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - bank-number + + additionalProperties: false + + "^func-[0-9a-z-]+$": + type: object + patternProperties: + "^group-[0-9a-z-]+$": + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + apb { + #address-cells = <2>; + #size-cells = <2>; + periphs_pinctrl: pinctrl { + compatible = "amlogic,pinctrl-a4"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio@14 { + reg = <0 0x14 0 0x10>, + <0 0x14 0 0x10>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + bank-number = ; + gpio-ranges = <&periphs_pinctrl 0 8 10>; + }; + + func-uart-b { + group-default { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + group-pins1 { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + + func-uart-c { + group-default { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + }; + }; diff --git a/include/dt-bindings/pinctrl/amlogic,pinctrl.h b/include/dt-bindings/pinctrl/amlogic,pinctrl.h new file mode 100644 index 000000000000..7d40aecc7147 --- /dev/null +++ b/include/dt-bindings/pinctrl/amlogic,pinctrl.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Xianwei Zhao + */ + +#ifndef _DT_BINDINGS_AMLOGIC_PINCTRL_H +#define _DT_BINDINGS_AMLOGIC_PINCTRL_H +/* Normal PIN bank */ +#define AMLOGIC_GPIO_A 0 +#define AMLOGIC_GPIO_B 1 +#define AMLOGIC_GPIO_C 2 +#define AMLOGIC_GPIO_D 3 +#define AMLOGIC_GPIO_E 4 +#define AMLOGIC_GPIO_F 5 +#define AMLOGIC_GPIO_G 6 +#define AMLOGIC_GPIO_H 7 +#define AMLOGIC_GPIO_I 8 +#define AMLOGIC_GPIO_J 9 +#define AMLOGIC_GPIO_K 10 +#define AMLOGIC_GPIO_L 11 +#define AMLOGIC_GPIO_M 12 +#define AMLOGIC_GPIO_N 13 +#define AMLOGIC_GPIO_O 14 +#define AMLOGIC_GPIO_P 15 +#define AMLOGIC_GPIO_Q 16 +#define AMLOGIC_GPIO_R 17 +#define AMLOGIC_GPIO_S 18 +#define AMLOGIC_GPIO_T 19 +#define AMLOGIC_GPIO_U 20 +#define AMLOGIC_GPIO_V 21 +#define AMLOGIC_GPIO_W 22 +#define AMLOGIC_GPIO_X 23 +#define AMLOGIC_GPIO_Y 24 +#define AMLOGIC_GPIO_Z 25 + +/* Special PIN bank */ +#define AMLOGIC_GPIO_DV 26 +#define AMLOGIC_GPIO_AO 27 +#define AMLOGIC_GPIO_CC 28 +#define AMLOGIC_GPIO_TEST_N 29 +#define AMLOGIC_GPIO_ANALOG 30 + +#define AML_PINMUX(bank, offset, mode) (((((bank) << 8) + (offset)) << 8) | (mode)) + +#endif /* _DT_BINDINGS_AMLOGIC_PINCTRL_H */