From patchwork Wed Jan 15 09:21:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Bruel X-Patchwork-Id: 13940120 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4332C02183 for ; Wed, 15 Jan 2025 09:29:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=T2NpMkqyrPPYgA6+mchmoxvpEASZ4QulelxEtrDC+Uw=; b=y9rNeuX1ui1jEnyMEzpeNhCebz OEUMi0GrCUyq+hlXhYXN0P/9Mc0Zfc7ruAbGYblKvpTM0yO8f3EheE8Z3AhgxViJFPuBD3BjTgCa0 u1MYk+aSBXP0S6ioLSiV1JFalgovBsesSRIyqB3XTita4bhnzqxWdkUx+afOen6UtdrOB3ZzZVceS BUOZAK/+VSaEpyCYAY/z7P3WLvq2OvzueJ1Z3qniH7TflOqIy9hur8nPOvo/SHuOQAEnSFqZZUgks SP4knudTg36jyF0FVqmZIE5HZQLZ03+8RAlzV3ftlJlTTAXCXohkDG1g29ekbZmk1N5bWtroIT/iY 4si06dFg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tXziB-0000000BK9x-1x6R; Wed, 15 Jan 2025 09:29:19 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tXzdQ-0000000BIqD-44fN for linux-arm-kernel@lists.infradead.org; Wed, 15 Jan 2025 09:24:26 +0000 Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50F9G1ox004499; Wed, 15 Jan 2025 10:24:08 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= T2NpMkqyrPPYgA6+mchmoxvpEASZ4QulelxEtrDC+Uw=; b=puvF9YzqKSGMaLRi t+8qT8Sxk5OVZ4zW+c5a03+0odLGkLzaJgTHDLHXLkP9Rxl5hw5HGvOOWbSlx1Ac ++MnocMF4w0Qlo82DnIkuvXzhva5oRSy3cSxeI+aUcRsWMVtp+3KXZYLDRvZ6hFo y+2V9x3z35uNydUFzFebmWUBPOmBwiJTJSYjCEP7SjDZggAbsWFCEAqabuwElIMB 6+6g7UeG0nfk1WvL3eEoDljBV5JzlinJyGTwA/Zloo+KWr5rBwQWFHwtpDlTs4E6 w684nbSrtecLJNfcEsbpXLGOQBaSPrD6/aGZPclJHcZPs/FY0dDu+aMsWI/4VoGY ohEZvQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 44637n9jk4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Jan 2025 10:24:07 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 8528940045; Wed, 15 Jan 2025 10:22:42 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3BC5C246443; Wed, 15 Jan 2025 10:22:42 +0100 (CET) Received: from localhost (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 15 Jan 2025 10:22:41 +0100 From: Christian Bruel To: , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v3 03/10] PCI: stm32: Add PCIe host support for STM32MP25 Date: Wed, 15 Jan 2025 10:21:27 +0100 Message-ID: <20250115092134.2904773-4-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250115092134.2904773-1-christian.bruel@foss.st.com> References: <20250115092134.2904773-1-christian.bruel@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.129.178.212] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-15_03,2025-01-15_02,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250115_012425_318057_958E27BE X-CRM114-Status: GOOD ( 26.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add driver for the STM32MP25 SoC PCIe Gen1 2.5 GT/s and Gen2 5GT/s controller based on the DesignWare PCIe core. Supports MSI via GICv2m, Single Virtual Channel, Single Function Supports wakeup-source from gpio wake_irq with dw_pcie_wake_irq_handler for host wakeup. Signed-off-by: Christian Bruel --- drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-stm32.c | 353 ++++++++++++++++++++++++ drivers/pci/controller/dwc/pcie-stm32.h | 15 + 4 files changed, 381 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-stm32.c create mode 100644 drivers/pci/controller/dwc/pcie-stm32.h diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index b6d6778b0698..0c18879b604c 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -389,6 +389,18 @@ config PCIE_SPEAR13XX help Say Y here if you want PCIe support on SPEAr13XX SoCs. +config PCIE_STM32 + tristate "STMicroelectronics STM32MP25 PCIe Controller (host mode)" + depends on ARCH_STM32 || COMPILE_TEST + depends on PCI_MSI + select PCIE_DW_HOST + help + Enables support for the DesignWare core based PCIe host controller + found in STM32MP25 SoC. + + This driver can also be built as a module. If so, the module + will be called pcie-stm32. + config PCI_DRA7XX tristate diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index a8308d9ea986..576d99cb3bc5 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o +obj-$(CONFIG_PCIE_STM32) += pcie-stm32.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-stm32.c b/drivers/pci/controller/dwc/pcie-stm32.c new file mode 100644 index 000000000000..05fba1b13b60 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-stm32.c @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STMicroelectronics STM32MP25 PCIe root complex driver. + * + * Copyright (C) 2024 STMicroelectronics + * Author: Christian Bruel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pcie-designware.h" +#include "pcie-stm32.h" +#include "../../pci.h" + +struct stm32_pcie { + struct dw_pcie pci; + struct regmap *regmap; + struct reset_control *rst; + struct phy *phy; + struct clk *clk; + struct gpio_desc *perst_gpio; + struct gpio_desc *wake_gpio; + unsigned int wake_irq; +}; + +static void stm32_pcie_deassert_perst(struct stm32_pcie *stm32_pcie) +{ + gpiod_set_value(stm32_pcie->perst_gpio, 0); + + if (stm32_pcie->perst_gpio) + msleep(PCIE_T_RRS_READY_MS); +} + +static void stm32_pcie_assert_perst(struct stm32_pcie *stm32_pcie) +{ + gpiod_set_value(stm32_pcie->perst_gpio, 1); +} + +static int stm32_pcie_start_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); + + return regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_LTSSM_EN, + STM32MP25_PCIECR_LTSSM_EN); +} + +static void stm32_pcie_stop_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); + + regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_LTSSM_EN, 0); +} + +static int stm32_pcie_suspend(struct device *dev) +{ + struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev); + + if (device_may_wakeup(dev)) + enable_irq_wake(stm32_pcie->wake_irq); + + return 0; +} + +static int stm32_pcie_resume(struct device *dev) +{ + struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev); + + if (device_may_wakeup(dev)) + disable_irq_wake(stm32_pcie->wake_irq); + + return 0; +} + +static int stm32_pcie_suspend_noirq(struct device *dev) +{ + struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev); + + stm32_pcie_stop_link(&stm32_pcie->pci); + + stm32_pcie_assert_perst(stm32_pcie); + + clk_disable_unprepare(stm32_pcie->clk); + + if (!device_may_wakeup(dev)) + phy_exit(stm32_pcie->phy); + + return pinctrl_pm_select_sleep_state(dev); +} + +static int stm32_pcie_resume_noirq(struct device *dev) +{ + struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev); + struct dw_pcie_rp *pp = &stm32_pcie->pci.pp; + int ret; + + /* + * The core clock is gated with CLKREQ# from the COMBOPHY REFCLK, + * thus if no device is present, must force it low with an init pinmux + * to be able to access the DBI registers. + */ + if (!IS_ERR(dev->pins->init_state)) + ret = pinctrl_select_state(dev->pins->p, dev->pins->init_state); + else + ret = pinctrl_pm_select_default_state(dev); + + if (ret) { + dev_err(dev, "Failed to activate pinctrl pm state: %d\n", ret); + return ret; + } + + if (!device_may_wakeup(dev)) { + ret = phy_init(stm32_pcie->phy); + if (ret) { + pinctrl_pm_select_default_state(dev); + return ret; + } + } + + ret = clk_prepare_enable(stm32_pcie->clk); + if (ret) + goto err_phy_exit; + + stm32_pcie_deassert_perst(stm32_pcie); + + ret = dw_pcie_setup_rc(pp); + if (ret) + goto err_disable_clk; + + ret = stm32_pcie_start_link(&stm32_pcie->pci); + if (ret) + goto err_disable_clk; + + /* Ignore errors, the link may come up later */ + dw_pcie_wait_for_link(&stm32_pcie->pci); + + pinctrl_pm_select_default_state(dev); + + return 0; + +err_disable_clk: + stm32_pcie_assert_perst(stm32_pcie); + clk_disable_unprepare(stm32_pcie->clk); + +err_phy_exit: + phy_exit(stm32_pcie->phy); + pinctrl_pm_select_default_state(dev); + + return ret; +} + +static const struct dev_pm_ops stm32_pcie_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_pcie_suspend_noirq, + stm32_pcie_resume_noirq) + SYSTEM_SLEEP_PM_OPS(stm32_pcie_suspend, stm32_pcie_resume) +}; + +static const struct dw_pcie_host_ops stm32_pcie_host_ops = { +}; + +static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = stm32_pcie_start_link, + .stop_link = stm32_pcie_stop_link +}; + +static int stm32_add_pcie_port(struct stm32_pcie *stm32_pcie, + struct platform_device *pdev) +{ + struct device *dev = stm32_pcie->pci.dev; + struct dw_pcie_rp *pp = &stm32_pcie->pci.pp; + int ret; + + ret = phy_set_mode(stm32_pcie->phy, PHY_MODE_PCIE); + if (ret) + return ret; + + ret = phy_init(stm32_pcie->phy); + if (ret) + return ret; + + ret = regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_TYPE_MASK, + STM32MP25_PCIECR_RC); + if (ret) + goto err_phy_exit; + + reset_control_assert(stm32_pcie->rst); + reset_control_deassert(stm32_pcie->rst); + + ret = clk_prepare_enable(stm32_pcie->clk); + if (ret) { + dev_err(dev, "Core clock enable failed %d\n", ret); + goto err_phy_exit; + } + + stm32_pcie_deassert_perst(stm32_pcie); + + pp->ops = &stm32_pcie_host_ops; + ret = dw_pcie_host_init(pp); + if (ret) { + dev_err(dev, "Failed to initialize host: %d\n", ret); + goto err_disable_clk; + } + + return 0; + +err_disable_clk: + clk_disable_unprepare(stm32_pcie->clk); + stm32_pcie_assert_perst(stm32_pcie); + +err_phy_exit: + phy_exit(stm32_pcie->phy); + + return ret; +} + +static int stm32_pcie_probe(struct platform_device *pdev) +{ + struct stm32_pcie *stm32_pcie; + struct device *dev = &pdev->dev; + struct device_node *root_port; + int ret; + + stm32_pcie = devm_kzalloc(dev, sizeof(*stm32_pcie), GFP_KERNEL); + if (!stm32_pcie) + return -ENOMEM; + + stm32_pcie->pci.dev = dev; + stm32_pcie->pci.ops = &dw_pcie_ops; + + stm32_pcie->regmap = syscon_regmap_lookup_by_compatible("st,stm32mp25-syscfg"); + if (IS_ERR(stm32_pcie->regmap)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->regmap), + "No syscfg specified\n"); + + root_port = of_get_next_available_child(dev->of_node, NULL); + stm32_pcie->phy = devm_of_phy_get(dev, root_port, "pcie-phy"); + if (IS_ERR(stm32_pcie->phy)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->phy), + "Failed to get pcie-phy\n"); + + stm32_pcie->clk = devm_clk_get(dev, NULL); + if (IS_ERR(stm32_pcie->clk)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->clk), + "Failed to get PCIe clock source\n"); + + stm32_pcie->rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(stm32_pcie->rst)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->rst), + "Failed to get PCIe reset\n"); + + stm32_pcie->perst_gpio = devm_gpiod_get_optional(dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(stm32_pcie->perst_gpio)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->perst_gpio), + "Failed to get reset GPIO\n"); + + platform_set_drvdata(pdev, stm32_pcie); + + if (device_property_read_bool(dev, "wakeup-source")) { + stm32_pcie->wake_gpio = devm_gpiod_get_optional(dev, "wake", + GPIOD_IN); + if (IS_ERR(stm32_pcie->wake_gpio)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->wake_gpio), + "Failed to get wake GPIO\n"); + } + + if (stm32_pcie->wake_gpio) { + stm32_pcie->wake_irq = gpiod_to_irq(stm32_pcie->wake_gpio); + + ret = devm_request_threaded_irq(&pdev->dev, + stm32_pcie->wake_irq, NULL, + dw_pcie_wake_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + "wake_irq", stm32_pcie->pci.dev); + + if (ret) + return dev_err_probe(dev, ret, "Failed to request WAKE IRQ: %d\n", ret); + } + + ret = devm_pm_runtime_enable(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable runtime PM %d\n", ret); + return ret; + } + + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_err(dev, "Failed to get runtime PM %d\n", ret); + return ret; + } + + ret = stm32_add_pcie_port(stm32_pcie, pdev); + if (ret) { + pm_runtime_put_sync(&pdev->dev); + return ret; + } + + if (stm32_pcie->wake_gpio) + device_set_wakeup_capable(dev, true); + + return 0; +} + +static void stm32_pcie_remove(struct platform_device *pdev) +{ + struct stm32_pcie *stm32_pcie = platform_get_drvdata(pdev); + struct dw_pcie_rp *pp = &stm32_pcie->pci.pp; + + if (stm32_pcie->wake_gpio) + device_init_wakeup(&pdev->dev, false); + + dw_pcie_host_deinit(pp); + + stm32_pcie_assert_perst(stm32_pcie); + + clk_disable_unprepare(stm32_pcie->clk); + + phy_exit(stm32_pcie->phy); + + pm_runtime_put_sync(&pdev->dev); +} + +static const struct of_device_id stm32_pcie_of_match[] = { + { .compatible = "st,stm32mp25-pcie-rc" }, + {}, +}; + +static struct platform_driver stm32_pcie_driver = { + .probe = stm32_pcie_probe, + .remove = stm32_pcie_remove, + .driver = { + .name = "stm32-pcie", + .of_match_table = stm32_pcie_of_match, + .pm = &stm32_pcie_pm_ops, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, +}; + +module_platform_driver(stm32_pcie_driver); + +MODULE_AUTHOR("Christian Bruel "); +MODULE_DESCRIPTION("STM32MP25 PCIe Controller driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, stm32_pcie_of_match); diff --git a/drivers/pci/controller/dwc/pcie-stm32.h b/drivers/pci/controller/dwc/pcie-stm32.h new file mode 100644 index 000000000000..3efd00937d3d --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-stm32.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * ST PCIe driver definitions for STM32-MP25 SoC + * + * Copyright (C) 2024 STMicroelectronics - All Rights Reserved + * Author: Christian Bruel + */ + +#define to_stm32_pcie(x) dev_get_drvdata((x)->dev) + +#define STM32MP25_PCIECR_TYPE_MASK GENMASK(11, 8) +#define STM32MP25_PCIECR_LTSSM_EN BIT(2) +#define STM32MP25_PCIECR_RC BIT(10) + +#define SYSCFG_PCIECR 0x6000