Message ID | 20250125011545.15547-3-zhangqing@rock-chips.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | clk: rockchip: Fixed some incorrect commits | expand |
Hi Elaine, On 2025-01-25 02:15, Elaine Zhang wrote: > This reverts commit 0f2ddb128fa20f8441d903285632f2c69e90fae1. > > Before changing the PLL frequency, in order to avoid overclocking the > child clock, set the child clock to a large div first, and then set the > CLK as required after the PLL is set. This commit message does not match what this patch does. In this patch you revert a change and in next patch you re-introduce same thing slightly different. As mentioned in v1, see [1], you should merge both patches as a single fix, if a fix really is needed. Testing on a rk3328-rock64 I see no difference before or after these changes. Please describe what this fixes because clk_summary show same clock tree and rates before and after this fix. Also for next revert patch you send, please include the patch author in the recipient list :-) [1] https://lore.kernel.org/all/cae9cb0a-1500-4fbc-bbf4-a6266549bcb9@kwiboo.se/ Regards, Jonas > > Fixes: 0f2ddb128fa2 ("arm64: dts: rockchip: Increase VOP clk rate on RK3328") > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > --- > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > index 7d992c3c01ce..f3ef8cbfbdae 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > @@ -852,8 +852,8 @@ > <0>, <24000000>, > <24000000>, <24000000>, > <15000000>, <15000000>, > - <300000000>, <100000000>, > - <400000000>, <100000000>, > + <100000000>, <100000000>, > + <100000000>, <100000000>, > <50000000>, <100000000>, > <100000000>, <100000000>, > <50000000>, <50000000>,
在 2025/1/26 5:39, Jonas Karlman 写道: > Hi Elaine, > > On 2025-01-25 02:15, Elaine Zhang wrote: >> This reverts commit 0f2ddb128fa20f8441d903285632f2c69e90fae1. >> >> Before changing the PLL frequency, in order to avoid overclocking the >> child clock, set the child clock to a large div first, and then set the >> CLK as required after the PLL is set. > This commit message does not match what this patch does. In this patch > you revert a change and in next patch you re-introduce same thing > slightly different. > > As mentioned in v1, see [1], you should merge both patches as a single > fix, if a fix really is needed. Ok, This will be fixed in the next release. > > Testing on a rk3328-rock64 I see no difference before or after these > changes. Please describe what this fixes because clk_summary show same > clock tree and rates before and after this fix. The clock tree might see the same result. It is not safe or correct to set the child clock frequency before setting the PLL frequency, and the parent clock PLL frequency may not be the final expected value at this time. Therefore, the correct setting of the child clock frequency should be after the PLL frequency is set. The partial clock is set before the PLL setting frequency, which is to prevent the child clock from overclocking when the PLL is set, so ensure that the child clock is at a safe frequency before setting the PLL, and reset the child clock frequency after the PLL is set. > > Also for next revert patch you send, please include the patch author in > the recipient list :-) > > [1] https://lore.kernel.org/all/cae9cb0a-1500-4fbc-bbf4-a6266549bcb9@kwiboo.se/ > > Regards, > Jonas > >> Fixes: 0f2ddb128fa2 ("arm64: dts: rockchip: Increase VOP clk rate on RK3328") >> >> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> >> --- >> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi >> index 7d992c3c01ce..f3ef8cbfbdae 100644 >> --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi >> +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi >> @@ -852,8 +852,8 @@ >> <0>, <24000000>, >> <24000000>, <24000000>, >> <15000000>, <15000000>, >> - <300000000>, <100000000>, >> - <400000000>, <100000000>, >> + <100000000>, <100000000>, >> + <100000000>, <100000000>, >> <50000000>, <100000000>, >> <100000000>, <100000000>, >> <50000000>, <50000000>, >
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 7d992c3c01ce..f3ef8cbfbdae 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -852,8 +852,8 @@ <0>, <24000000>, <24000000>, <24000000>, <15000000>, <15000000>, - <300000000>, <100000000>, - <400000000>, <100000000>, + <100000000>, <100000000>, + <100000000>, <100000000>, <50000000>, <100000000>, <100000000>, <100000000>, <50000000>, <50000000>,
This reverts commit 0f2ddb128fa20f8441d903285632f2c69e90fae1. Before changing the PLL frequency, in order to avoid overclocking the child clock, set the child clock to a large div first, and then set the CLK as required after the PLL is set. Fixes: 0f2ddb128fa2 ("arm64: dts: rockchip: Increase VOP clk rate on RK3328") Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)