| Message ID | 20250131093531.1054924-1-w.egorov@phytec.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] arm64: dts: ti: k3-am64-phycore-som: Reserve RTOS IPC memory | expand |
Hi Wadim Egorov, On Fri, 31 Jan 2025 10:35:30 +0100, Wadim Egorov wrote: > Reserve a portion of memory for inter-processor communication between > all remote processors running RTOS or baremetal firmware. > > I have applied the following to branch ti-next on [1]. Thank you! [1/2] arm64: dts: ti: k3-am64-phycore-som: Reserve RTOS IPC memory commit: eeab4a777eb490b9eca670379720b938226b1c79 [2/2] arm64: dts: ti: k3-am62-phycore-som: Reserve RTOS IPC memory commit: 4ad59ca98c2764ee2a58e48c96338b6fb88ce85a All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. [1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git -- Vignesh
diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 99a6fdfaa7fb..e8d1b88651e7 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -99,6 +99,12 @@ mcu_m4fss_memory_region: m4f-memory@a4100000 { reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; leds {
Reserve a portion of memory for inter-processor communication between all remote processors running RTOS or baremetal firmware. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> --- arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)