From patchwork Wed Feb 5 10:05:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Faizal Rahim X-Patchwork-Id: 13960779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8C55C02192 for ; Wed, 5 Feb 2025 10:21:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To: Cc:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=kiAvYVDX8B7kq38LtgH4TWg6/8ud9sT8B+p6r6RMXRw=; b=V95hPqRunj7FwR4lUXD9+kf2BR nvbNi94xRLuWLJHfL62eF8g0wlCros6yL0yHxsDG/q2Zrai46h6BvCiyx7KZlPlt0eDZp8b8sr2P1 lpueP+7RPS+KMi2nmK5/4hD427iI8nlw3xItV4fMJiC8dKWGOmC9TOgD+jE5JWrewJkigE/vZmNmi AoLZFhlDVCp4WS6GKahWknzGd/Bn9wiLYPWKdig4v6874WAYji2yASOs3h8Qzi58cPsENSMF39BAS NfY45KeGEchDys3Zqxbksgr8A/uhKqyhicEAhwjKrqc3iK/c+4q+wU1bftog6QGvF/FUVxD8yfTER P3cCj/Bw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfcX8-00000002rM3-16Gi; Wed, 05 Feb 2025 10:21:26 +0000 Received: from mgamail.intel.com ([198.175.65.12]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfcIg-00000002oZJ-0umE for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2025 10:06:31 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738749990; x=1770285990; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=E8DpF0MkqsXjGVAc4bco9kOfLMJgtadeevV01g23TiY=; b=mn9n73DUG5VgmTAOD78ruHCtLaFkLS1i8vM/tclg7PL4+8Qb1m3ra/xa 056aC37H8rmzHafQQ+ITF487DIzaowxlPv1/4hhTtOhWtKJNaaIgGyCs8 A2G+HnqKAo2gQGSstobbbEVVpvbXXUzRGY0Vnys/tGxdMvKLTT6L9AMBK 1xTsrSCOO5Y1L8aF+OVfDTXZdFBFKKTs1NtyqzyRCyGqokshbgHNPg7JE ALNYl1SFfZO5B9UhG9IzvswablEn1qXSch1kuCAUfr1Qzv34MZpDqWrkB J8lBEwaMqlWavbHB0jYoInYYQjIq0jNQAkV7xn7CkiqZwhgrKt6ADs2AV A==; X-CSE-ConnectionGUID: JQaiun3sS/uaQqWiS/Vcgw== X-CSE-MsgGUID: 9F/Pcr5PRkmYkCajcWmd9w== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="50699216" X-IronPort-AV: E=Sophos;i="6.13,261,1732608000"; d="scan'208";a="50699216" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2025 02:06:29 -0800 X-CSE-ConnectionGUID: yXDs+qaCQx66dLDA3HHQHg== X-CSE-MsgGUID: hyV+bh6RSda7mX52BhO2mA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="111297756" Received: from mohdfai2-ilbpg12-1.png.intel.com ([10.88.227.73]) by orviesa007.jf.intel.com with ESMTP; 05 Feb 2025 02:06:22 -0800 From: Faizal Rahim To: Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Simon Horman , Russell King , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Russell King , Furong Xu <0x1207@gmail.com>, Vladimir Oltean , Serge Semin , Xiaolei Wang , Suraj Jaiswal , Kory Maincent , Petr Tesarik , Faizal Rahim , Choong Yong Liang , Kunihiko Hayashi , Vinicius Costa Gomes , intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, bpf@vger.kernel.org Subject: [PATCH iwl-next v2 7/9] igc: Add support for preemptible traffic class in taprio Date: Wed, 5 Feb 2025 05:05:22 -0500 Message-Id: <20250205100524.1138523-8-faizal.abdul.rahim@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205100524.1138523-1-faizal.abdul.rahim@linux.intel.com> References: <20250205100524.1138523-1-faizal.abdul.rahim@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_020630_306156_8373EB05 X-CRM114-Status: GOOD ( 18.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Set queue as preemptible or express for taprio. This will eventually set queue-specific preemptible field in TXQCTL register. Verified that the correct preemptible hardware queue is set using the following commands: a) 1:1 TC-to-Queue Mapping $ sudo tc qdisc replace dev enp1s0 parent root handle 100 \ taprio num_tc 4 map 3 2 1 0 3 3 3 3 3 3 3 3 3 3 3 3 \ queues 1@0 1@1 1@2 1@3 base-time 0 sched-entry S F 100000 \ fp E E P P b) Non-1:1 TC-to-Queue Mapping $ sudo tc qdisc replace dev enp1s0 parent root handle 100 \ taprio num_tc 3 map 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 2 queues 2@0 1@2 1@3 fp E E P Co-developed-by: Vinicius Costa Gomes Signed-off-by: Vinicius Costa Gomes Signed-off-by: Faizal Rahim --- drivers/net/ethernet/intel/igc/igc.h | 2 +- drivers/net/ethernet/intel/igc/igc_defines.h | 1 + drivers/net/ethernet/intel/igc/igc_main.c | 36 ++++++++++++++++++++ drivers/net/ethernet/intel/igc/igc_tsn.c | 4 +++ 4 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h index 2f3662143589..e9f7a75aef13 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -163,7 +163,7 @@ struct igc_ring { bool launchtime_enable; /* true if LaunchTime is enabled */ ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */ ktime_t last_ff_cycle; /* Last cycle with an active first flag */ - + bool preemptible; /* True if not express */ u32 start_time; u32 end_time; u32 max_sdu; diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h index 9d7d903545ed..d7b4f5b6e548 100644 --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h @@ -559,6 +559,7 @@ #define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001 #define IGC_TXQCTL_STRICT_CYCLE 0x00000002 #define IGC_TXQCTL_STRICT_END 0x00000004 +#define IGC_TXQCTL_PREEMPTIBLE 0x00000008 #define IGC_TXQCTL_QAV_SEL_MASK 0x000000C0 #define IGC_TXQCTL_QAV_SEL_CBS0 0x00000080 #define IGC_TXQCTL_QAV_SEL_CBS1 0x000000C0 diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c index 396410522e01..6f7f4c641393 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -6254,6 +6254,39 @@ static bool is_base_time_past(ktime_t base_time, const struct timespec64 *now) return timespec64_compare(now, &b) > 0; } +static u32 igc_map_tc_to_queue(const struct igc_adapter *adapter, + unsigned long preemptible_tcs) +{ + struct net_device *dev = adapter->netdev; + u32 i, queue = 0; + + for (i = 0; i < dev->num_tc; i++) { + u32 offset, count; + + if (!(preemptible_tcs & BIT(i))) + continue; + + offset = dev->tc_to_txq[i].offset; + count = dev->tc_to_txq[i].count; + queue |= GENMASK(offset + count - 1, offset); + } + + return queue; +} + +static void igc_save_preempt_queue(struct igc_adapter *adapter, + const struct tc_mqprio_qopt_offload *mqprio) +{ + u32 preemptible_queue = igc_map_tc_to_queue(adapter, + mqprio->preemptible_tcs); + + for (int i = 0; i < adapter->num_tx_queues; i++) { + struct igc_ring *tx_ring = adapter->tx_ring[i]; + + tx_ring->preemptible = preemptible_queue & BIT(i); + } +} + static bool validate_schedule(struct igc_adapter *adapter, const struct tc_taprio_qopt_offload *qopt) { @@ -6340,6 +6373,7 @@ static int igc_qbv_clear_schedule(struct igc_adapter *adapter) ring->start_time = 0; ring->end_time = NSEC_PER_SEC; ring->max_sdu = 0; + ring->preemptible = false; } spin_lock_irqsave(&adapter->qbv_tx_lock, flags); @@ -6496,6 +6530,8 @@ static int igc_save_qbv_schedule(struct igc_adapter *adapter, ring->max_sdu = 0; } + igc_save_preempt_queue(adapter, &qopt->mqprio); + return 0; } diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c b/drivers/net/ethernet/intel/igc/igc_tsn.c index 50c343c59e29..61ad464ed053 100644 --- a/drivers/net/ethernet/intel/igc/igc_tsn.c +++ b/drivers/net/ethernet/intel/igc/igc_tsn.c @@ -459,6 +459,10 @@ static int igc_tsn_enable_offload(struct igc_adapter *adapter) if (ring->launchtime_enable) txqctl |= IGC_TXQCTL_QUEUE_MODE_LAUNCHT; + if (ethtool_mmsv_is_tx_active(&adapter->fpe.mmsv) && + ring->preemptible) + txqctl |= IGC_TXQCTL_PREEMPTIBLE; + /* Skip configuring CBS for Q2 and Q3 */ if (i > 1) goto skip_cbs;