From patchwork Thu Feb 6 15:49:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13963284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6466EC02194 for ; Thu, 6 Feb 2025 15:58:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=kzZPwS+0OSiBGJdEXWvJFNaLRU3jzdcwxGBemC/KgK4=; b=ieMSkgAJg/dCdP0xTqQ8oQFHPf F8WEodjst3L2dbsKXdelXdfZjGy9vza/t5GDdWdC0tiBQ6Pdk+HIm48lkGDE+BupVR6mzcYJjgRtz tas2K7WcOaWWFRd0P5aob9mBjxIWRZd0kbcP/7/DQ9MIe5loNrKx9Mox4j0c8CMkt4RW/d6aF0nNV aIvKfy2j7oVxVOoH3ffmm5jwPAIM388q4o09AZlfBhmIPjz0Sjy3ozkTUDWy+HdbY5veJdYxJwwwD 1pPnXUKnN9UYcpgJCZtDIkQoAd5ZAUka+pAsJ6etBsDbIHALButcfyPLB5E6uFAvp/j0kMqQgl7K5 y3GtOtmA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tg4GT-00000006mLL-1Miz; Thu, 06 Feb 2025 15:58:05 +0000 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tg48M-00000006kw0-3S4b for linux-arm-kernel@lists.infradead.org; Thu, 06 Feb 2025 15:49:45 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 0147AA4213A; Thu, 6 Feb 2025 15:47:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A107AC4CEDF; Thu, 6 Feb 2025 15:49:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738856981; bh=yuFlDaL+lICxdp2tle8fmEhBUnWIS+5Z4d11toXNzuA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pTta+TLUZ+DOnotpeB9kVMojMOO4QFntWokJgWzDFBOECJrOuc6YG6AljZt8+KxZr /pxFM98e+dWs8BhQWbLFg/q5UCvKv5ZKrE4+gOyaSIAbeGmxFxC9AqiQx+rL7RZAk1 95UDX6nAzsVdEMp0PaAbixKcKoB6JQLQIXK4DfPoVZSLMZm6/hQBN9WBXH0av59iY7 qqtvZSHQ0rbXgStPywa7Q0MuV/ob86whSkGuwhXvT7pjA0S+tnArQ7lGXzwNv7KrPL JXLIzDEdLNx+bphfMg45iHb+aeP+HCGoiXTp3LW97lG73ii2AtA+IYpWPSCJtxjdHA 259mnKV/T9yTw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tg48J-001BOX-Kd; Thu, 06 Feb 2025 15:49:39 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Andre Przywara , Eric Auger Subject: [PATCH v3 03/16] arm64: sysreg: Add layout for ICH_MISR_EL2 Date: Thu, 6 Feb 2025 15:49:12 +0000 Message-Id: <20250206154925.1109065-4-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250206154925.1109065-1-maz@kernel.org> References: <20250206154925.1109065-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, andre.przywara@arm.com, eric.auger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250206_074942_991547_050A209B X-CRM114-Status: UNSURE ( 9.47 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The ICH_MISR_EL2-related macros are missing a number of status bits that we are about to handle. Take this opportunity to fully describe the layout of that register as part of the automatic generation infrastructure. Reviewed-by: Andre Przywara Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/sysreg.h | 5 ----- arch/arm64/tools/sysreg | 12 ++++++++++++ tools/arch/arm64/include/asm/sysreg.h | 5 ----- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b59b2c680e977..9511f3faac462 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -562,7 +562,6 @@ #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) -#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) @@ -983,10 +982,6 @@ #define SYS_MPIDR_SAFE_VAL (BIT(31)) /* GIC Hypervisor interface registers */ -/* ICH_MISR_EL2 bit definitions */ -#define ICH_MISR_EOI (1 << 0) -#define ICH_MISR_U (1 << 1) - /* ICH_LR*_EL2 bit definitions */ #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 3e82a072eb493..2c63662c1a489 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3071,6 +3071,18 @@ Res0 17:5 Field 4:0 ListRegs EndSysreg +Sysreg ICH_MISR_EL2 3 4 12 11 2 +Res0 63:8 +Field 7 VGrp1D +Field 6 VGrp1E +Field 5 VGrp0D +Field 4 VGrp0E +Field 3 NP +Field 2 LRENP +Field 1 U +Field 0 EOI +EndSysreg + Sysreg CONTEXTIDR_EL2 3 4 13 0 1 Fields CONTEXTIDR_ELx EndSysreg diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h index 5d9d7e394b254..b6c5ece4fdee7 100644 --- a/tools/arch/arm64/include/asm/sysreg.h +++ b/tools/arch/arm64/include/asm/sysreg.h @@ -558,7 +558,6 @@ #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) -#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) @@ -979,10 +978,6 @@ #define SYS_MPIDR_SAFE_VAL (BIT(31)) /* GIC Hypervisor interface registers */ -/* ICH_MISR_EL2 bit definitions */ -#define ICH_MISR_EOI (1 << 0) -#define ICH_MISR_U (1 << 1) - /* ICH_LR*_EL2 bit definitions */ #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)