@@ -175,10 +175,11 @@
#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
#define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
-/* ISS definitions for LD64B/ST64B instructions */
+/* ISS definitions for LD64B/ST64B/PSBCSYNC instructions */
#define ESR_ELx_ISS_ST64BV (0)
#define ESR_ELx_ISS_ST64BV0 (1)
#define ESR_ELx_ISS_LDST64B (2)
+#define ESR_ELx_ISS_PSBCSYNC (3)
#define DISR_EL1_IDS (UL(1) << 24)
/*
@@ -1996,6 +1996,7 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
/* Additional FGTs that do not fire with ESR_EL2.EC==0x18 */
static const union trap_config non_0x18_fgt[] __initconst = {
+ FGT(HFGITR, PSBCSYNC, 1),
FGT(HFGITR, nGCSSTR_EL1, 0),
FGT(HFGITR, SVC_EL1, 1),
FGT(HFGITR, SVC_EL0, 1),
@@ -321,6 +321,9 @@ static int handle_ls64b(struct kvm_vcpu *vcpu)
case ESR_ELx_ISS_LDST64B:
allowed = kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64);
break;
+ case ESR_ELx_ISS_PSBCSYNC:
+ allowed = kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P5);
+ break;
default:
/* Clearly, we're missing something. */
goto unknown_trap;
@@ -343,6 +346,9 @@ static int handle_ls64b(struct kvm_vcpu *vcpu)
case ESR_ELx_ISS_LDST64B:
fwd = !(hcrx & HCRX_EL2_EnALS);
break;
+ case ESR_ELx_ISS_PSBCSYNC:
+ fwd = (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_PSBCSYNC);
+ break;
default:
/* We don't expect to be here */
fwd = false;
@@ -2560,7 +2560,7 @@ Fields HFGxTR_EL2
EndSysreg
Sysreg HFGITR_EL2 3 4 1 1 6
-Res0 63
+Field 63 PSBCSYNC
Field 62 ATS1E1A
Res0 61
Field 60 COSPRCTX
Bizarrely, the architecture introduces a trap for PSB CSYNC that has the same EC as LS64. Let's deal with this oddity and add specific handling for it. It's not that we expect this to be useful any time soon anyway. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/include/asm/esr.h | 3 ++- arch/arm64/kvm/emulate-nested.c | 1 + arch/arm64/kvm/handle_exit.c | 6 ++++++ arch/arm64/tools/sysreg | 2 +- 4 files changed, 10 insertions(+), 2 deletions(-)