| Message ID | 20250218211044.2256762-1-heiko@sntech.de (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] arm64: dts: rockchip: add usb typec host support to rk3588-jaguar | expand |
Hi Heiko, On 2/18/25 10:10 PM, Heiko Stuebner wrote: [...] > @@ -483,6 +583,16 @@ pcie30x4_waken_m0: pcie30x4-waken-m0 { > rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; > }; > }; > + > + usb3 { > + cc_int1: cc-int1 { > + rockchip,pins = <4 RK_PA3 0 &pcfg_pull_up>; We actually already have an external HW pull-up for that, see R221 (and R227 for CC_INT2). They are pulled up to the same power rail than VDD of the FUSB IC so there shouldn't be any issue with an interrupt spuriously triggering because the power rail isn't enabled early enough. Shouldn't we use RK_GPIO instead of 0? > + }; > + > + cc_int2: cc-int2 { > + rockchip,pins = <4 RK_PA4 0 &pcfg_pull_up>; Ditto. [...] > +&usbdp_phy0 { > + orientation-switch; > + sbu1-dc-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU1_DC */ > + sbu2-dc-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU2_DC */ > + status = "okay"; > + > + port { > + #address-cells = <1>; > + #size-cells = <0>; > + > + usbdp_phy0_typec_ss: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&usbc0_ss>; > + }; > + > + usbdp_phy0_typec_sbu: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&usbc0_sbu>; > + }; > + }; > +}; > + > +&usbdp_phy1 { > + orientation-switch; > + sbu1-dc-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU1_DC */ > + sbu2-dc-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU2_DC */ Maybe pinctrl for those too :) ? Ditto for usbdp_phy0 above. Can we have a comment above usbdp_phy0 to say it's for P11? Ditto for P12? Looks ok to me otherwise, will start some build to test this on my Jaguar to give my T-b tag while you work on the v3 :) Cheers, Quentin
Hi Heiko, On 2/18/25 10:10 PM, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@cherry.de> > > Jaguar has two type-c ports connected to fusb302 controllers that can > work both in host and device mode and can also run in display-port > altmode. > > While these ports can work in dual-role data mode, they do not support > powering the device itself as power-sink. This causes issues because > the current infrastructure does not cope well with dual-role data > without dual-role power. > > So add the necessary nodes for the type-c controllers as well > as enable the relevant core usb nodes, but limit the mode to host-mode > for now until we figure out device mode. > > Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> While the USB functionality does work for both ports, and the orientation is properly reported, it seems like there may be some issue with how the PHY or controller interacts with that info because I do not get USB3 speeds when the device is inserted in reverse orientation, while I do when it's in normal orientation. I assume that's the case for the Rock 5 ITX and Orange Pi 5+ as well and probably has nothing to do with the DT? Should we go still go on with trying to merge this patch knowing that? I mean USB2 is still better than no USB at all :) +Cc Chen-Yu, owner of an Orange Pi 5+, who may be able to confirm the issue is widespread. Cheers, Quentin
Am Freitag, 21. Februar 2025, 17:43:08 MEZ schrieb Quentin Schulz: > Hi Heiko, > > On 2/18/25 10:10 PM, Heiko Stuebner wrote: > > From: Heiko Stuebner <heiko.stuebner@cherry.de> > > > > Jaguar has two type-c ports connected to fusb302 controllers that can > > work both in host and device mode and can also run in display-port > > altmode. > > > > While these ports can work in dual-role data mode, they do not support > > powering the device itself as power-sink. This causes issues because > > the current infrastructure does not cope well with dual-role data > > without dual-role power. > > > > So add the necessary nodes for the type-c controllers as well > > as enable the relevant core usb nodes, but limit the mode to host-mode > > for now until we figure out device mode. > > > > Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> > > While the USB functionality does work for both ports, and the > orientation is properly reported, it seems like there may be some issue > with how the PHY or controller interacts with that info because I do not > get USB3 speeds when the device is inserted in reverse orientation, > while I do when it's in normal orientation. I've tested both ports and saw the issue too. Interestingly on the usbdp-phy side, orientation detection seems correct and also the sbu pins are set accordingly. > I assume that's the case for the Rock 5 ITX and Orange Pi 5+ as well and > probably has nothing to do with the DT? > > Should we go still go on with trying to merge this patch knowing that? I > mean USB2 is still better than no USB at all :) > > +Cc Chen-Yu, owner of an Orange Pi 5+, who may be able to confirm the > issue is widespread. > > Cheers, > Quentin >
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index ef56380530f9..48059d9b3ad6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -333,6 +333,56 @@ rtc_twi: rtc@6f { }; }; + typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cc_int1>; + vbus-supply = <&vcc_5v0_usb_c1>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USBC-1 P11"; + power-role = "source"; + self-powered; + source-pdos = + <PDO_FIXED(5000, 1500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM)>; + vbus-supply = <&vcc_5v0_usb_c1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; + vdd_npu_s0: regulator@42 { compatible = "rockchip,rk8602"; reg = <0x42>; @@ -394,6 +444,56 @@ &i2c8 { pinctrl-0 = <&i2c8m2_xfer>; status = "okay"; + typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cc_int2>; + vbus-supply = <&vcc_5v0_usb_c2>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USBC-2 P12"; + power-role = "source"; + self-powered; + source-pdos = + <PDO_FIXED(5000, 1500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM)>; + vbus-supply = <&vcc_5v0_usb_c2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc1_hs: endpoint { + remote-endpoint = <&usb_host1_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + usbc1_ss: endpoint { + remote-endpoint = <&usbdp_phy1_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc1_sbu: endpoint { + remote-endpoint = <&usbdp_phy1_typec_sbu>; + }; + }; + }; + }; + }; + vdd_cpu_big0_s0: regulator@42 { compatible = "rockchip,rk8602"; reg = <0x42>; @@ -483,6 +583,16 @@ pcie30x4_waken_m0: pcie30x4-waken-m0 { rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; }; }; + + usb3 { + cc_int1: cc-int1 { + rockchip,pins = <4 RK_PA3 0 &pcfg_pull_up>; + }; + + cc_int2: cc-int2 { + rockchip,pins = <4 RK_PA4 0 &pcfg_pull_up>; + }; + }; }; &saradc { @@ -851,6 +961,24 @@ &tsadc { status = "okay"; }; +/* USB-C P11 connector */ +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +/* USB-C P12 connector */ +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -893,6 +1021,50 @@ &uart7 { status = "okay"; }; +&usbdp_phy0 { + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU1_DC */ + sbu2-dc-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU2_DC */ + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + +&usbdp_phy1 { + orientation-switch; + sbu1-dc-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU1_DC */ + sbu2-dc-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU2_DC */ + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy1_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc1_ss>; + }; + + usbdp_phy1_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc1_sbu>; + }; + }; +}; + /* host0 on P10 USB-A */ &usb_host0_ehci { status = "okay"; @@ -903,6 +1075,38 @@ &usb_host0_ohci { status = "okay"; }; +/* host0 on P11 USB-C */ +&usb_host0_xhci { + /* The port-hw supports DRD, but needs more work */ + dr_mode = "host"; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + +/* host1 on P12 USB-C */ +&usb_host1_xhci { + /* The port-hw supports DRD, but needs more work */ + dr_mode = "host"; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host1_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc1_hs>; + }; + }; +}; + /* host1 on M.2 E-key */ &usb_host1_ehci { status = "okay";