@@ -109,6 +109,17 @@ properties:
power-domains:
maxItems: 1
+ mediatek,pbus-csr:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to pbus-csr syscon
+ - description: offset of pbus-csr base address register
+ - description: offset of pbus-csr base address mask register
+ description:
+ Phandle with two arguments to the syscon node used to detect if
+ a given address is accessible on PCIe controller.
+
'#interrupt-cells':
const: 1
@@ -168,6 +179,8 @@ allOf:
minItems: 1
maxItems: 2
+ mediatek,pbus-csr: false
+
- if:
properties:
compatible:
@@ -197,6 +210,8 @@ allOf:
minItems: 1
maxItems: 2
+ mediatek,pbus-csr: false
+
- if:
properties:
compatible:
@@ -224,6 +239,8 @@ allOf:
minItems: 1
maxItems: 2
+ mediatek,pbus-csr: false
+
- if:
properties:
compatible:
Introduce the mediatek,pbus-csr property for the pbus-csr syscon node available on EN7581 SoC. The airoha pbus-csr block provides a configuration interface for the PBUS controller used to detect if a given address is accessible on PCIe controller. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> --- .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)