From patchwork Sun Feb 23 09:31:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13986903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A76F2C021B3 for ; Sun, 23 Feb 2025 09:40:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+KpwD9DSAohTavwKVdbGP/4nmZ1gc4KlbuZ5A2rjutU=; b=4timQ0pBwNthT4pFbGHKFZ3V0p kppOF9luYq6k2foKVS132mEzRLQVu+d2JJs/RDVBqcMf3yzIykXdfGLHdnI9nYzB72kdexSyYRsdM 1vM+Bf02dwvUJJiKadtTAi39hXIMYzSV7cTS5dkwp4vJ/dFH+3gsSbBV7c07WeXjzTH8l+eWykuKC xMddvBwCPHd92EndH7ennJSm+NlR6PvN6iQMf/Gacc4ryL9mABlQ9voLi2iHL1YiFAPpIQblwBzjY CAr6n1PzABU5Qv1CcblfR10WVuF2TB2iV8UvJRPOVSMBHbNndVSeDdYu2yY+LzVkWTGiqQNvfjqOa Ddoa7W4A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tm8TR-0000000AnCG-3xrf; Sun, 23 Feb 2025 09:40:33 +0000 Received: from bali.collaboradmins.com ([2a01:4f8:201:9162::2]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tm8Lm-0000000AliP-2eAO; Sun, 23 Feb 2025 09:32:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1740303157; bh=SE9Nutny/gzjaQ3Hy7tTClTNDcn3VFJaaCAjW0BhTsc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=UDWClHbfy2lN7RQStexxDn+njHyDLp5ChxksGKP7Uo4hoN1O9ET9J2nJGyn2kBzOH 5ZvtdzIxClimUtlIFtc7X36VbXAc99XC+beTZ3eGOc9GGRl9h3nF6HS7ZiS/S+kHJq RnsmpncGqbWnrtld2L6pHI46l+tEuEiF0EWVrQeoTWVMJuRh6DGIQDyJ5EH1BkE7g6 EtIKWEoTkXUZQcqY1Y7kHXN+gaXmkoXg3UguWTu49nFGJqManXvTVCIHK8QMrfFzJT MO4MrEsneQyJIbrEJQ9S3KlMxr/nZqbASNHxs1s1RLKH13F6g6RYKmvauWJ0WT2Dkz Jmd3sdOV8ns6g== Received: from localhost (unknown [188.27.58.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 2EC4717E0CFA; Sun, 23 Feb 2025 10:32:37 +0100 (CET) From: Cristian Ciocaltea Date: Sun, 23 Feb 2025 11:31:40 +0200 Subject: [PATCH v2 4/5] arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588 MIME-Version: 1.0 Message-Id: <20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com> References: <20250223-vop2-hdmi1-disp-modes-v2-0-f4cec5e06fbe@collabora.com> In-Reply-To: <20250223-vop2-hdmi1-disp-modes-v2-0-f4cec5e06fbe@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250223_013238_818003_FDE62BFF X-CRM114-Status: GOOD ( 10.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and more accurate pixel clock source to improve handling of display modes up to 4K@60Hz on video ports 0, 1 and 2. The HDMI1 PHY PLL clock source cannot be added directly to vop node in rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an optional feature and its PHY node belongs to a separate (extra) DT file. Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its clocks & clock-names properties in the extra DT file. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 97e55990e0524ed447d182cef416190822bf67be..1df8845bdc264b07601add3747b273f92091e7fa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -542,3 +542,24 @@ pcie30phy: phy@fee80000 { status = "disabled"; }; }; + +&vop { + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>, + <&hdptxphy0>, + <&hdptxphy1>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop", + "pll_hdmiphy0", + "pll_hdmiphy1"; +};