From patchwork Thu Feb 27 12:24:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13994421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2355BC021BE for ; Thu, 27 Feb 2025 13:14:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DMy9dUkJU56DJTvhIPb2QmSzWfdgvdoGZhrFNGotouU=; b=E0dvEVWNc1PtZz8dE30EjdVbbm J2b2PL7kn/RCW/I+NS0krvZm6trzQnaxx2NU6klXc3FDVRdkWbAJ+/xbe7U0R/9MPN25VonkgVKKl aYDx/G+Ts2fC4x8h2NAvUSPXaoiz21EPh2yYkqMQ3A3lJQz9qhTX7oC+MyRD7csD6wMmcGE7IchpQ Zn3Eju24St4jkkjGUSv5uyn0cbFRw8UcaW7h70Mk4jHKyYUVUyzAXUvR3ZraLpZ7/aAPU/zrpoEXx i5FNrqD7Qbx+Bi/MUDKV8dmsk1jjBepcUtvpfaO8CJMsW+pAS6itVxe0cbGIbjyTW8EvyZy1qKxG9 J2/jMKuQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tndid-00000007TtD-18HF; Thu, 27 Feb 2025 13:14:27 +0000 Received: from relmlor2.renesas.com ([210.160.252.172] helo=relmlie6.idc.renesas.com) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tncxa-00000007MTH-3aZr for linux-arm-kernel@lists.infradead.org; Thu, 27 Feb 2025 12:25:52 +0000 X-CSE-ConnectionGUID: g6Vaue9kS5qa2+4g9N+WzA== X-CSE-MsgGUID: YJ4Ty9v5QdG0ExfWErAv4g== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 27 Feb 2025 21:25:50 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.68]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 019F64007D01; Thu, 27 Feb 2025 21:25:42 +0900 (JST) From: John Madieu To: john.madieu.xa@bp.renesas.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, catalin.marinas@arm.com, will@kernel.org Cc: john.madieu@gmail.com, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, biju.das.jz@bp.renesas.com Subject: [PATCH v2 6/7] arm64: dts: renesas: r9a09g047: Add TSU node Date: Thu, 27 Feb 2025 13:24:42 +0100 Message-ID: <20250227122453.30480-7-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227122453.30480-1-john.madieu.xa@bp.renesas.com> References: <20250227122453.30480-1-john.madieu.xa@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250227_042551_009509_DE32923C X-CRM114-Status: UNSURE ( 9.18 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. Signed-off-by: John Madieu --- v1 -> v2: Fix IRQ names arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index a6b83e057a40..93b57d7ad7b9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -64,6 +64,7 @@ cpu0: cpu@0 { next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -74,6 +75,7 @@ cpu1: cpu@100 { next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -84,6 +86,7 @@ cpu2: cpu@200 { next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -94,6 +97,7 @@ cpu3: cpu@300 { next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -302,6 +306,20 @@ wdt3: watchdog@13000400 { status = "disabled"; }; + tsu: thermal@14002000 { + compatible = "renesas,r9a09g047-tsu"; + reg = <0 0x14002000 0 0x1000>; + interrupts = , + ; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 0x10a>; + resets = <&cpg 0xf8>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + renesas,tsu-operating-mode = <0>; + renesas,tsu-calibration-sys = <&sys>; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; @@ -502,6 +520,37 @@ gic: interrupt-controller@14900000 { }; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution = <1024>; + }; + }; + + trips { + target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor_crit: sensor-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,