| Message ID | 20250305130026.642219-7-faizal.abdul.rahim@linux.intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | igc: Add support for Frame Preemption feature in IGC | expand |
On Wed, Mar 05, 2025 at 08:00:21AM -0500, Faizal Rahim wrote: > In preparation for supporting frame preemption, when entering TSN mode > set the receive packet buffer to 16KB for the Express MAC, 16KB for > the Preemptible MAC and 2KB for the BMC, according to the datasheet > section 7.1.3.2. > > Co-developed-by: Vinicius Costa Gomes <vinicius.gomes@intel.com> > Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com> > Signed-off-by: Faizal Rahim <faizal.abdul.rahim@linux.intel.com> > --- > drivers/net/ethernet/intel/igc/igc_defines.h | 3 +++ > drivers/net/ethernet/intel/igc/igc_tsn.c | 13 +++++++++++-- > 2 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h > index 516ef70c98e9..b19ac6f30dac 100644 > --- a/drivers/net/ethernet/intel/igc/igc_defines.h > +++ b/drivers/net/ethernet/intel/igc/igc_defines.h > @@ -402,6 +402,9 @@ > > /* 7KB bytes buffer for each tx queue (total 4 queues) + 4KB for BMC*/ > #define IGC_TXPBSIZE_TSN 0x041c71c7 > +/* 15KB for EXP + 15KB for BE + 2KB for BMC */ > +#define IGC_RXPBSIZE_TSN 0x0000f08f > +#define IGC_RXPBSIZE_SIZE_MASK 0x0001FFFF Does 0x0000f08f have any further meaning, does it represent anything bitwise? (similar question for IGC_TXPBSIZE_TSN in the previous patch). I don't see the correlation between the values mentioned in the comment and the magic constant. If RXPBPSIZE has a bitwise meaning, maybe you could rewrite the magic value with macros for each field.
diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h index 516ef70c98e9..b19ac6f30dac 100644 --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h @@ -402,6 +402,9 @@ /* 7KB bytes buffer for each tx queue (total 4 queues) + 4KB for BMC*/ #define IGC_TXPBSIZE_TSN 0x041c71c7 +/* 15KB for EXP + 15KB for BE + 2KB for BMC */ +#define IGC_RXPBSIZE_TSN 0x0000f08f +#define IGC_RXPBSIZE_SIZE_MASK 0x0001FFFF #define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */ #define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */ diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c b/drivers/net/ethernet/intel/igc/igc_tsn.c index 1e44374ca1ff..f0213cfce07d 100644 --- a/drivers/net/ethernet/intel/igc/igc_tsn.c +++ b/drivers/net/ethernet/intel/igc/igc_tsn.c @@ -132,13 +132,17 @@ static int igc_tsn_disable_offload(struct igc_adapter *adapter) { u16 queue_per_tc[4] = { 3, 2, 1, 0 }; struct igc_hw *hw = &adapter->hw; - u32 tqavctrl; + u32 tqavctrl, rxpbs; int i; wr32(IGC_GTXOFFSET, 0); wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT); wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_DEFAULT); + rxpbs = rd32(IGC_RXPBS) & ~IGC_RXPBSIZE_SIZE_MASK; + rxpbs |= I225_RXPBSIZE_DEFAULT; + wr32(IGC_RXPBS, rxpbs); + if (igc_is_device_id_i226(hw)) igc_tsn_restore_retx_default(adapter); @@ -194,7 +198,7 @@ static int igc_tsn_enable_offload(struct igc_adapter *adapter) { struct igc_hw *hw = &adapter->hw; u32 tqavctrl, baset_l, baset_h; - u32 sec, nsec, cycle; + u32 sec, nsec, cycle, rxpbs; ktime_t base_time, systim; int i; @@ -202,6 +206,11 @@ static int igc_tsn_enable_offload(struct igc_adapter *adapter) wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_TSN); wr32(IGC_TXPBS, IGC_TXPBSIZE_TSN); + rxpbs = rd32(IGC_RXPBS) & ~IGC_RXPBSIZE_SIZE_MASK; + rxpbs |= IGC_RXPBSIZE_TSN; + + wr32(IGC_RXPBS, rxpbs); + if (igc_is_device_id_i226(hw)) igc_tsn_set_retx_qbvfullthreshold(adapter);