From patchwork Wed Mar 5 19:45:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Zi X-Patchwork-Id: 14003435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA4E8C19F32 for ; Wed, 5 Mar 2025 21:33:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=E60PMdBi2EuO85vVyPJfNYg118xZrAs+xmQPB3P7CUA=; b=eiROzZamtHy97gi1kVegq/7fP6 Kp4DTaaMzT7wXB41qsVBhqbjVDTqNdT3q8rtNldSmGRm2KcYmUH8zPa3tRDXyFphmS6Nn2HfRpxkf xqU9ejjKWkVtFeiP0ObZ4FZYSFiMdHq/6lMT+WFFypW/IlKk+RUk/Lc63hHiqk7Tk34m0vJN3WciM 1pps4Pbqx36PY7OoVyzPS0Kgz1oNp9FolagisipSzb9ntst3AcfEdRn59TOjiBZ/hB6gfL0Zl7vb4 3goab+k0RUwwTQ1NkXCrbfKXe0F7Z5DRnd9zyP2i0v/HobKQZ9JWkXUM8SMgsdfPBQSrOa5lQ7PlR Wr/vsopg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpwN9-00000009MPb-3K38; Wed, 05 Mar 2025 21:33:47 +0000 Received: from layka.disroot.org ([178.21.23.139]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpuh2-0000000972K-238v; Wed, 05 Mar 2025 19:46:13 +0000 Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 3E9F02531A; Wed, 5 Mar 2025 20:46:11 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id cYil4KX2Hwuh; Wed, 5 Mar 2025 20:46:06 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1741203966; bh=R4aIj3VtgP3nzRQODwLmtHA8je9xAP+QLEm/30cUmmY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=JKF943m2r/RcCtYecED58Aa3AyJLTt1QwBpTAaWpqPx0UpRv99NFmhJu0GXEG1990 GxYLFVZfLXK5AO4sJhA3sRgnTl6pBhhejdJNck/NCYYETqyciBibHdAgNgiUTaTJkZ LbMrftGZU3hybWl9gOACPlvGucOk9LwcyZXCCjgjgEpoczRBrsKXahgEhK9lW2x0jM lllqWPHEWb6GjlV4X7B0jpmdPI0dCsEjlRB9aunxpqg2Jtd6EVC0zZ/jT5P3f7WtFA JtP2udhoY5lRD7xGGjrdH3mpbBKgV8ejCblXJWPeMjXSrYIXlzUumwkitZeMzaOLWt /WXcpUOScGRgw== From: Yao Zi To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Michael Turquette , Stephen Boyd , Shresth Prasad , Cristian Ciocaltea , Detlev Casanova , Jonas Karlman , Chukun Pan Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Yao Zi Subject: [PATCH v2 6/8] clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region Date: Wed, 5 Mar 2025 19:45:44 +0000 Message-ID: <20250305194544.47155-1-ziyao@disroot.org> In-Reply-To: <20250305194217.47052-1-ziyao@disroot.org> References: <20250305194217.47052-1-ziyao@disroot.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250305_114612_792163_898A7B4D X-CRM114-Status: GOOD ( 15.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org These clocks locate in VO and VPU GRF, serving for SD/SDIO controller tuning purpose. Add their definitions and register them in driver if corresponding GRF is available. GRFs are looked up by compatible to simplify devicetree binding. Signed-off-by: Yao Zi --- drivers/clk/rockchip/clk-rk3528.c | 61 ++++++++++++++++++++++++++++--- drivers/clk/rockchip/clk.h | 3 ++ 2 files changed, 58 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3528.c b/drivers/clk/rockchip/clk-rk3528.c index b8b577b902a0..5c133a642ff9 100644 --- a/drivers/clk/rockchip/clk-rk3528.c +++ b/drivers/clk/rockchip/clk-rk3528.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include @@ -1061,23 +1063,64 @@ static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = { 0, 1, 1), }; +static struct rockchip_clk_branch rk3528_vo_clk_branches[] __initdata = { + MMC_GRF(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc0", + RK3528_SDMMC_CON(0), 1), + MMC_GRF(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc0", + RK3528_SDMMC_CON(1), 1), +}; + +static struct rockchip_clk_branch rk3528_vpu_clk_branches[] __initdata = { + MMC_GRF(SCLK_SDIO0_DRV, "sdio0_drv", "cclk_src_sdio0", + RK3528_SDIO0_CON(0), 1), + MMC_GRF(SCLK_SDIO0_SAMPLE, "sdio0_sample", "cclk_src_sdio0", + RK3528_SDIO0_CON(1), 1), + MMC_GRF(SCLK_SDIO1_DRV, "sdio1_drv", "cclk_src_sdio1", + RK3528_SDIO1_CON(0), 1), + MMC_GRF(SCLK_SDIO1_SAMPLE, "sdio1_sample", "cclk_src_sdio1", + RK3528_SDIO1_CON(1), 1), +}; + static int __init clk_rk3528_probe(struct platform_device *pdev) { - struct rockchip_clk_provider *ctx; + unsigned long nr_vpu_branches = ARRAY_SIZE(rk3528_vpu_clk_branches); + unsigned long nr_vo_branches = ARRAY_SIZE(rk3528_vo_clk_branches); + unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches); + unsigned long nr_clks, nr_vo_clks, nr_vpu_clks; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; - unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches); - unsigned long nr_clks; + struct rockchip_clk_provider *ctx; + struct regmap *vo_grf, *vpu_grf; void __iomem *reg_base; - nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches, - nr_branches) + 1; - reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(reg_base)) return dev_err_probe(dev, PTR_ERR(reg_base), "could not map cru region"); + nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches, + nr_branches) + 1; + + vo_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vo-grf"); + if (!IS_ERR(vo_grf)) { + nr_vo_clks = rockchip_clk_find_max_clk_id(rk3528_vo_clk_branches, + nr_vo_branches) + 1; + nr_clks = max(nr_clks, nr_vo_clks); + } else if (PTR_ERR(vo_grf) != -ENODEV) { + return dev_err_probe(dev, PTR_ERR(vo_grf), + "failed to look up VO GRF\n"); + } + + vpu_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vpu-grf"); + if (!IS_ERR(vpu_grf)) { + nr_vpu_clks = rockchip_clk_find_max_clk_id(rk3528_vpu_clk_branches, + nr_vpu_branches) + 1; + nr_clks = max(nr_clks, nr_vpu_clks); + } else if (PTR_ERR(vpu_grf) != -ENODEV) { + return dev_err_probe(dev, PTR_ERR(vpu_grf), + "failed to look up VPU GRF\n"); + } + ctx = rockchip_clk_init(np, reg_base, nr_clks); if (IS_ERR(ctx)) return dev_err_probe(dev, PTR_ERR(ctx), @@ -1091,6 +1134,12 @@ static int __init clk_rk3528_probe(struct platform_device *pdev) &rk3528_cpuclk_data, rk3528_cpuclk_rates, ARRAY_SIZE(rk3528_cpuclk_rates)); rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches); + if (!IS_ERR(vo_grf)) + rockchip_clk_register_grf_branches(ctx, rk3528_vo_clk_branches, + vo_grf, nr_vo_branches); + if (!IS_ERR(vpu_grf)) + rockchip_clk_register_grf_branches(ctx, rk3528_vpu_clk_branches, + vpu_grf, nr_vpu_branches); rk3528_rst_init(np, reg_base); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index ec86ba1dd38c..f07cd1bb8952 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -217,6 +217,9 @@ struct clk; #define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) #define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800) #define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3528_SDMMC_CON(x) ((x) * 0x4 + 0x24) +#define RK3528_SDIO0_CON(x) ((x) * 0x4 + 0x4) +#define RK3528_SDIO1_CON(x) ((x) * 0x4 + 0xc) #define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) #define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE) #define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)