From patchwork Wed Mar 5 20:26:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 14003376 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8DABCC19F32 for ; Wed, 5 Mar 2025 21:09:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=4XWVS9/h7eUhXMxOax2+CnPIZod/3R8T0gLmA/LtLm8=; b=Y4fsJbub8uLFg9gYrV8nltTsr1 wYId5lTk82nqvAbvuMY7i7uAZkxnq3Zhg//DYXzb3u7UlkReSXZqybNPAwEXagqoxcWAewH7MCGu1 jjLRq3FMobB3zq6qtykK+iEhooOG6dQufx6ar/RP1TKR5gqp2mT4ibL/9sV99eevk/bqED8lfGzks jqZo++4sxL/Eaq6idBpwyxqprlyzhm7cX/dVpVtPWRyYBWRE+v9QOOL0f/8tBmPX1iGJddzqz24jl /9ib8ncDLX2uhMdA8xGWowx6v6pESWqdMR9DzntYFUfUhnYkoE55iZ6GFnw3vifg6xmT/WIGnNRQ6 Mc/eCN7g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpvzF-00000009J8a-2Xpm; Wed, 05 Mar 2025 21:09:05 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpvKe-00000009D71-3Oif for linux-arm-kernel@bombadil.infradead.org; Wed, 05 Mar 2025 20:27:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=4XWVS9/h7eUhXMxOax2+CnPIZod/3R8T0gLmA/LtLm8=; b=DMIxaPgRY2AN1lN5iLhuWD72Sl nO5OiCkZFn+1xxb0yP0Bra6W0ZGSSdxtJxOBKzrTjnUE2z9SgnfPQxUCfHqM6ow9CsnsOQCpIbvw5 swy3SPlsn9xiJyUbLAdHk9pvdJzhjRdxyYqD8XlpZDNsKlDZM3FUXsGy9TQx4Lq0OzL1Id0C6j46k +k7nqAws0uuLh990BR4SoK4pQ23pzJrw35gXLyDK9b/XII2mE9aw+e56/pTi+CJ2jcZx9B+bueV4Y Uw0ew2tGONXixMxCbIjU2A7GIhDbMMPJD26OUYCkyhsPbLZZuabc9f7QYFPKGhry6fxgg9PzwKt/r 5/P0imNQ==; Received: from out-186.mta1.migadu.com ([95.215.58.186]) by casper.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpvKb-00000006AQj-2r4y for linux-arm-kernel@lists.infradead.org; Wed, 05 Mar 2025 20:27:07 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1741206416; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4XWVS9/h7eUhXMxOax2+CnPIZod/3R8T0gLmA/LtLm8=; b=ES663g1dDnkMivbNztk2hVTJxrnDvBc8jnOjIiMy2ncZEhv+/00XeFJ9Ani/p0B738uY6s +fHq/x/R/6eYwaPqLdrVsjPoXyz6+XO9ScS2h9F7B+6bTZMfsN3mnkD88cb+uYXiCwqW+C 1O3IfEuOkTwOR3KQUfJ9pwcZokfdfQ4= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Janne Grunau , Oliver Upton Subject: [PATCH v3 01/14] drivers/perf: apple_m1: Refactor event select/filter configuration Date: Wed, 5 Mar 2025 12:26:28 -0800 Message-Id: <20250305202641.428114-2-oliver.upton@linux.dev> In-Reply-To: <20250305202641.428114-1-oliver.upton@linux.dev> References: <20250305202641.428114-1-oliver.upton@linux.dev> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250305_202705_747117_B7312BB8 X-CRM114-Status: GOOD ( 10.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Supporting guest mode events will necessitate programming two event filters. Prepare by splitting up the programming of the event selector + event filter into separate headers. Opportunistically replace RMW patterns with sysreg_clear_set_s(). Tested-by: Janne Grunau Signed-off-by: Oliver Upton --- drivers/perf/apple_m1_cpu_pmu.c | 52 ++++++++++++++++++++------------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index 06fd317529fc..cea80afd1253 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -327,11 +327,10 @@ static void m1_pmu_disable_counter_interrupt(unsigned int index) __m1_pmu_enable_counter_interrupt(index, false); } -static void m1_pmu_configure_counter(unsigned int index, u8 event, - bool user, bool kernel) +static void __m1_pmu_configure_event_filter(unsigned int index, bool user, + bool kernel) { - u64 val, user_bit, kernel_bit; - int shift; + u64 clear, set, user_bit, kernel_bit; switch (index) { case 0 ... 7: @@ -346,19 +345,24 @@ static void m1_pmu_configure_counter(unsigned int index, u8 event, BUG(); } - val = read_sysreg_s(SYS_IMP_APL_PMCR1_EL1); - + clear = set = 0; if (user) - val |= user_bit; + set |= user_bit; else - val &= ~user_bit; + clear |= user_bit; if (kernel) - val |= kernel_bit; + set |= kernel_bit; else - val &= ~kernel_bit; + clear |= kernel_bit; - write_sysreg_s(val, SYS_IMP_APL_PMCR1_EL1); + sysreg_clear_set_s(SYS_IMP_APL_PMCR1_EL1, clear, set); +} + +static void __m1_pmu_configure_eventsel(unsigned int index, u8 event) +{ + u64 clear = 0, set = 0; + int shift; /* * Counters 0 and 1 have fixed events. For anything else, @@ -371,21 +375,29 @@ static void m1_pmu_configure_counter(unsigned int index, u8 event, break; case 2 ... 5: shift = (index - 2) * 8; - val = read_sysreg_s(SYS_IMP_APL_PMESR0_EL1); - val &= ~((u64)0xff << shift); - val |= (u64)event << shift; - write_sysreg_s(val, SYS_IMP_APL_PMESR0_EL1); + clear |= (u64)0xff << shift; + set |= (u64)event << shift; + sysreg_clear_set_s(SYS_IMP_APL_PMESR0_EL1, clear, set); break; case 6 ... 9: shift = (index - 6) * 8; - val = read_sysreg_s(SYS_IMP_APL_PMESR1_EL1); - val &= ~((u64)0xff << shift); - val |= (u64)event << shift; - write_sysreg_s(val, SYS_IMP_APL_PMESR1_EL1); + clear |= (u64)0xff << shift; + set |= (u64)event << shift; + sysreg_clear_set_s(SYS_IMP_APL_PMESR1_EL1, clear, set); break; } } +static void m1_pmu_configure_counter(unsigned int index, unsigned long config_base) +{ + bool kernel = config_base & M1_PMU_CFG_COUNT_KERNEL; + bool user = config_base & M1_PMU_CFG_COUNT_USER; + u8 evt = config_base & M1_PMU_CFG_EVENT; + + __m1_pmu_configure_event_filter(index, user, kernel); + __m1_pmu_configure_eventsel(index, evt); +} + /* arm_pmu backend */ static void m1_pmu_enable_event(struct perf_event *event) { @@ -400,7 +412,7 @@ static void m1_pmu_enable_event(struct perf_event *event) m1_pmu_disable_counter(event->hw.idx); isb(); - m1_pmu_configure_counter(event->hw.idx, evt, user, kernel); + m1_pmu_configure_counter(event->hw.idx, event->hw.config_base); m1_pmu_enable_counter(event->hw.idx); m1_pmu_enable_counter_interrupt(event->hw.idx); isb();