| Message ID | 20250306150017.488975-2-amadeus@jmu.edu.cn (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: rockchip: enable SCMI clk for RK3528 SoC | expand |
Hi Chukun, On 2025-03-06 16:00, Chukun Pan wrote: > Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK. > Add SCMI clk for CPU, GPU and RNG will also use it. > > Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> > --- > arch/arm64/boot/dts/rockchip/rk3528.dtsi | 33 ++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > index b1713ed4d7e2..476b83f98834 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > @@ -59,6 +59,9 @@ cpu0: cpu@0 { > reg = <0x0>; > device_type = "cpu"; > enable-method = "psci"; > + clocks = <&scmi_clk SCMI_CLK_CPU>; > + assigned-clocks = <&scmi_clk SCMI_CLK_CPU>; > + assigned-clock-rates = <1200000000>; This is new compared to v1, please add operating-points instead. cpu_pvtpll is already initialized to 1.2 GHz by firmware, see e.g. [1]. [1] https://lore.kernel.org/u-boot/20250123224844.3104592-5-jonas@kwiboo.se/ Regards, Jonas > }; > > cpu1: cpu@1 { > @@ -66,6 +69,7 @@ cpu1: cpu@1 { > reg = <0x1>; > device_type = "cpu"; > enable-method = "psci"; > + clocks = <&scmi_clk SCMI_CLK_CPU>; > }; > > cpu2: cpu@2 { > @@ -73,6 +77,7 @@ cpu2: cpu@2 { > reg = <0x2>; > device_type = "cpu"; > enable-method = "psci"; > + clocks = <&scmi_clk SCMI_CLK_CPU>; > }; > > cpu3: cpu@3 { > @@ -80,6 +85,22 @@ cpu3: cpu@3 { > reg = <0x3>; > device_type = "cpu"; > enable-method = "psci"; > + clocks = <&scmi_clk SCMI_CLK_CPU>; > + }; > + }; > + > + firmware { > + scmi: scmi { > + compatible = "arm,scmi-smc"; > + arm,smc-id = <0x82000010>; > + shmem = <&scmi_shmem>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + scmi_clk: protocol@14 { > + reg = <0x14>; > + #clock-cells = <1>; > + }; > }; > }; > > @@ -88,6 +109,18 @@ psci { > method = "smc"; > }; > > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + scmi_shmem: shmem@10f000 { > + compatible = "arm,scmi-shmem"; > + reg = <0x0 0x0010f000 0x0 0x100>; > + no-map; > + }; > + }; > + > timer { > compatible = "arm,armv8-timer"; > interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index b1713ed4d7e2..476b83f98834 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -59,6 +59,9 @@ cpu0: cpu@0 { reg = <0x0>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPU>; + assigned-clock-rates = <1200000000>; }; cpu1: cpu@1 { @@ -66,6 +69,7 @@ cpu1: cpu@1 { reg = <0x1>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu2: cpu@2 { @@ -73,6 +77,7 @@ cpu2: cpu@2 { reg = <0x2>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu3: cpu@3 { @@ -80,6 +85,22 @@ cpu3: cpu@3 { reg = <0x3>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; }; }; @@ -88,6 +109,18 @@ psci { method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK. Add SCMI clk for CPU, GPU and RNG will also use it. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+)