| Message ID | 20250306221402.1704196-4-jonas@kwiboo.se (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | rockchip: Enable Ethernet controller on Radxa E20C | expand |
On Thu, Mar 06, 2025 at 10:13:56PM +0000, Jonas Karlman wrote: > Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC > Ethernet QoS IP. > > Add device tree nodes for the two Ethernet controllers in RK3528. > > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> > --- > gmac0 is missing the integrated-phy and has not been tested bacause I do > not have any board that use this Ethernet controller. What do you know about the integrated PHY? Does it use one of the standard phy-modes? RMII? Does the datasheet indicate what address it uses on the MDIO bus? If you know these two bits of information, you can probably add it. Andrew
Hi Andrew, On 2025-03-06 23:46, Andrew Lunn wrote: > On Thu, Mar 06, 2025 at 10:13:56PM +0000, Jonas Karlman wrote: >> Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC >> Ethernet QoS IP. >> >> Add device tree nodes for the two Ethernet controllers in RK3528. >> >> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> >> --- >> gmac0 is missing the integrated-phy and has not been tested bacause I do >> not have any board that use this Ethernet controller. > > What do you know about the integrated PHY? Does it use one of the > standard phy-modes? RMII? Does the datasheet indicate what address it > uses on the MDIO bus? If you know these two bits of information, you > can probably add it. The SoC datasheet lists following: MAC 10/100/1000 Ethernet Controller (gmac1) - Support 10/100/1000 Mbps data transfer rates with the RGMII interfaces - Support 10/100 Mbps data transfer rates with the RMII interfaces - Support both full-duplex and half-duplex operation - Supports IEEE 802.1Q VLAN tag detection for reception frames - Support detection of LAN wake-up frames and AMD Magic Packet frames - Support checking IPv4 header checksum and TCP, UDP, or ICMP checksum encapsulated in IPv4 or IPv6 datagram - Support for TCP Segmentation Offload (TSO) and UDP Fragmentation Offload (UFO) MAC 10/100M Ethernet controller and MAC PHY (gmac0) - Support one Ethernet controllers - Support 10/100-Mbps data transfer rates with the RMII interfaces - Support both full-duplex and half-duplex operation and vendor kernel use following DT node: phy-mode = "rmii"; clock_in_out = "input"; phy-handle = <&rmii0_phy>; mdio0: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <0x1>; #size-cells = <0x0>; rmii0_phy: ethernet-phy@2 { compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22"; reg = <2>; clocks = <&cru CLK_MACPHY>; resets = <&cru SRST_MACPHY>; phy-is-integrated; pinctrl-names = "default"; pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>; }; }; I could possible add something like that to the device tree, or I could drop the entire gmac0 node and instead have it added in a future series. Regards, Jonas > > Andrew
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index c1a71ea81e03..5940719cffec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -286,6 +286,98 @@ saradc: adc@ffae0000 { #io-channel-cells = <1>; }; + gmac0: ethernet@ffbd0000 { + compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xffbd0000 0x0 0x10000>; + clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>, + <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>, + <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>; + clock-names = "stmmaceth", "clk_mac_ref", + "mac_clk_rx", "mac_clk_tx", + "pclk_mac", "aclk_mac"; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&cru SRST_A_MAC_VO>; + reset-names = "stmmaceth"; + rockchip,grf = <&vo_grf>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <8>; + snps,wr_osr_lmt = <4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + gmac1: ethernet@ffbe0000 { + compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xffbe0000 0x0 0x10000>; + clocks = <&cru CLK_GMAC1_SRC_VPU>, + <&cru CLK_GMAC1_RMII_VPU>, + <&cru PCLK_MAC_VPU>, + <&cru ACLK_MAC_VPU>; + clock-names = "stmmaceth", + "clk_mac_ref", + "pclk_mac", + "aclk_mac"; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&cru SRST_A_MAC>; + reset-names = "stmmaceth"; + rockchip,grf = <&vpu_grf>; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <8>; + snps,wr_osr_lmt = <4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + sdhci: mmc@ffbf0000 { compatible = "rockchip,rk3528-dwcmshc", "rockchip,rk3588-dwcmshc";
Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC Ethernet QoS IP. Add device tree nodes for the two Ethernet controllers in RK3528. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- gmac0 is missing the integrated-phy and has not been tested bacause I do not have any board that use this Ethernet controller. --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 92 ++++++++++++++++++++++++ 1 file changed, 92 insertions(+)