[16/26] clk: mediatek: Add MT8196 mdpsys clock support

Message ID	20250307032942.10447-17-guangjie.song@mediatek.com (mailing list archive)
State	New
Headers	show Return-Path: <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org> From: Guangjie Song <guangjie.song@mediatek.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Richard Cochran <richardcochran@gmail.com> CC: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <netdev@vger.kernel.org>, Guangjie Song <guangjie.song@mediatek.com>, <Project_Global_Chrome_Upstream_Group@mediatek.com> Subject: [PATCH 16/26] clk: mediatek: Add MT8196 mdpsys clock support Date: Fri, 7 Mar 2025 11:27:12 +0800 Message-ID: <20250307032942.10447-17-guangjie.song@mediatek.com> In-Reply-To: <20250307032942.10447-1-guangjie.song@mediatek.com> References: <20250307032942.10447-1-guangjie.song@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
Series	clk: mediatek: Add MT8196 clock support \| expand [00/26] clk: mediatek: Add MT8196 clock support [01/26] clk: mediatek: Add defines for vote [02/26] clk: mediatek: Support voting for pll [03/26] clk: mediatek: Support voting for mux [04/26] clk: mediatek: Support voting for gate [05/26] clk: mediatek: Add gate ops without disable [06/26] dt-bindings: clock: mediatek: Add new MT8196 clock [07/26] clk: mediatek: Add MT8196 apmixedsys clock support [08/26] clk: mediatek: Add MT8196 apmixedsys_gp2 clock support [09/26] clk: mediatek: Add MT8196 topckgen clock support [10/26] clk: mediatek: Add MT8196 topckgen2 clock support [11/26] clk: mediatek: Add MT8196 vlpckgen clock support [12/26] clk: mediatek: Add MT8196 peripheral clock support [13/26] clk: mediatek: Add MT8196 adsp clock support [14/26] clk: mediatek: Add MT8196 i2c clock support [15/26] clk: mediatek: Add MT8196 mcu clock support [16/26] clk: mediatek: Add MT8196 mdpsys clock support [17/26] clk: mediatek: Add MT8196 mfg clock support [18/26] clk: mediatek: Add MT8196 disp0 clock support [19/26] clk: mediatek: Add MT8196 disp1 clock support [20/26] clk: mediatek: Add MT8196 disp-ao clock support [21/26] clk: mediatek: Add MT8196 ovl0 clock support [22/26] clk: mediatek: Add MT8196 ovl1 clock support [23/26] clk: mediatek: Add MT8196 pextpsys clock support [24/26] clk: mediatek: Add MT8196 ufssys clock support [25/26] clk: mediatek: Add MT8196 vdecsys clock support [26/26] clk: mediatek: Add MT8196 vencsys clock support

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 4473feebae40..8763cc1480a3 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -1031,6 +1031,13 @@ config COMMON_CLK_MT8196_MCUSYS help This driver supports MediaTek MT8196 mcusys clocks. +config COMMON_CLK_MT8196_MDPSYS + tristate "Clock driver for MediaTek MT8196 mdpsys" + depends on COMMON_CLK_MT8196 + default COMMON_CLK_MT8196 + help + This driver supports MediaTek MT8196 mdpsys clocks. + config COMMON_CLK_MT8365 tristate "Clock driver for MediaTek MT8365" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 1f6717569609..dccc6d84941c 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -156,6 +156,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-apmixedsys obj-$(CONFIG_COMMON_CLK_MT8196_ADSP) += clk-mt8196-adsp.o obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o +obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o diff --git a/drivers/clk/mediatek/clk-mt8196-mdpsys.c b/drivers/clk/mediatek/clk-mt8196-mdpsys.c new file mode 100644 index 000000000000..ef591efa9fec --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8196-mdpsys.c @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Guangjie Song <guangjie.song@mediatek.com> + */ + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include <dt-bindings/clock/mt8196-clk.h> +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +static const struct mtk_gate_regs mdp10_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs mdp11_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +static const struct mtk_gate_regs mdp12_cg_regs = { + .set_ofs = 0x124, + .clr_ofs = 0x128, + .sta_ofs = 0x120, +}; + +#define GATE_MDP10(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &mdp10_cg_regs, \ + .shift = _shift, \ + .flags = CLK_OPS_PARENT_ENABLE, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_MDP10_V(_id, _name, _parent) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &cg_regs_dummy, \ + .ops = &mtk_clk_dummy_ops, \ + } + +#define GATE_MDP11(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &mdp11_cg_regs, \ + .shift = _shift, \ + .flags = CLK_OPS_PARENT_ENABLE, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_MDP11_V(_id, _name, _parent) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &cg_regs_dummy, \ + .ops = &mtk_clk_dummy_ops, \ + } + +#define GATE_MDP12(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &mdp12_cg_regs, \ + .shift = _shift, \ + .flags = CLK_OPS_PARENT_ENABLE, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_MDP12_V(_id, _name, _parent) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &cg_regs_dummy, \ + .ops = &mtk_clk_dummy_ops, \ + } + +static const struct mtk_gate mdp1_clks[] = { + /* MDP10 */ + GATE_MDP10(CLK_MDP1_MDP_MUTEX0, "mdp1_mdp_mutex0", "ck2_mdp_ck", 0), + GATE_MDP10_V(CLK_MDP1_MDP_MUTEX0_MML, "mdp1_mdp_mutex0_mml", "mdp1_mdp_mutex0"), + GATE_MDP10(CLK_MDP1_SMI0, "mdp1_smi0", "ck2_mdp_ck", 1), + GATE_MDP10_V(CLK_MDP1_SMI0_SMI, "mdp1_smi0_smi", "mdp1_smi0"), + GATE_MDP10(CLK_MDP1_APB_BUS, "mdp1_apb_bus", "ck2_mdp_ck", 2), + GATE_MDP10_V(CLK_MDP1_APB_BUS_MML, "mdp1_apb_bus_mml", "mdp1_apb_bus"), + GATE_MDP10(CLK_MDP1_MDP_RDMA0, "mdp1_mdp_rdma0", "ck2_mdp_ck", 3), + GATE_MDP10_V(CLK_MDP1_MDP_RDMA0_MML, "mdp1_mdp_rdma0_mml", "mdp1_mdp_rdma0"), + GATE_MDP10(CLK_MDP1_MDP_RDMA1, "mdp1_mdp_rdma1", "ck2_mdp_ck", 4), + GATE_MDP10_V(CLK_MDP1_MDP_RDMA1_MML, "mdp1_mdp_rdma1_mml", "mdp1_mdp_rdma1"), + GATE_MDP10(CLK_MDP1_MDP_RDMA2, "mdp1_mdp_rdma2", "ck2_mdp_ck", 5), + GATE_MDP10_V(CLK_MDP1_MDP_RDMA2_MML, "mdp1_mdp_rdma2_mml", "mdp1_mdp_rdma2"), + GATE_MDP10(CLK_MDP1_MDP_BIRSZ0, "mdp1_mdp_birsz0", "ck2_mdp_ck", 6), + GATE_MDP10_V(CLK_MDP1_MDP_BIRSZ0_MML, "mdp1_mdp_birsz0_mml", "mdp1_mdp_birsz0"), + GATE_MDP10(CLK_MDP1_MDP_HDR0, "mdp1_mdp_hdr0", "ck2_mdp_ck", 7), + GATE_MDP10_V(CLK_MDP1_MDP_HDR0_MML, "mdp1_mdp_hdr0_mml", "mdp1_mdp_hdr0"), + GATE_MDP10(CLK_MDP1_MDP_AAL0, "mdp1_mdp_aal0", "ck2_mdp_ck", 8), + GATE_MDP10_V(CLK_MDP1_MDP_AAL0_MML, "mdp1_mdp_aal0_mml", "mdp1_mdp_aal0"), + GATE_MDP10(CLK_MDP1_MDP_RSZ0, "mdp1_mdp_rsz0", "ck2_mdp_ck", 9), + GATE_MDP10_V(CLK_MDP1_MDP_RSZ0_MML, "mdp1_mdp_rsz0_mml", "mdp1_mdp_rsz0"), + GATE_MDP10(CLK_MDP1_MDP_RSZ2, "mdp1_mdp_rsz2", "ck2_mdp_ck", 10), + GATE_MDP10_V(CLK_MDP1_MDP_RSZ2_MML, "mdp1_mdp_rsz2_mml", "mdp1_mdp_rsz2"), + GATE_MDP10(CLK_MDP1_MDP_TDSHP0, "mdp1_mdp_tdshp0", "ck2_mdp_ck", 11), + GATE_MDP10_V(CLK_MDP1_MDP_TDSHP0_MML, "mdp1_mdp_tdshp0_mml", "mdp1_mdp_tdshp0"), + GATE_MDP10(CLK_MDP1_MDP_COLOR0, "mdp1_mdp_color0", "ck2_mdp_ck", 12), + GATE_MDP10_V(CLK_MDP1_MDP_COLOR0_MML, "mdp1_mdp_color0_mml", "mdp1_mdp_color0"), + GATE_MDP10(CLK_MDP1_MDP_WROT0, "mdp1_mdp_wrot0", "ck2_mdp_ck", 13), + GATE_MDP10_V(CLK_MDP1_MDP_WROT0_MML, "mdp1_mdp_wrot0_mml", "mdp1_mdp_wrot0"), + GATE_MDP10(CLK_MDP1_MDP_WROT1, "mdp1_mdp_wrot1", "ck2_mdp_ck", 14), + GATE_MDP10_V(CLK_MDP1_MDP_WROT1_MML, "mdp1_mdp_wrot1_mml", "mdp1_mdp_wrot1"), + GATE_MDP10(CLK_MDP1_MDP_WROT2, "mdp1_mdp_wrot2", "ck2_mdp_ck", 15), + GATE_MDP10_V(CLK_MDP1_MDP_WROT2_MML, "mdp1_mdp_wrot2_mml", "mdp1_mdp_wrot2"), + GATE_MDP10(CLK_MDP1_MDP_FAKE_ENG0, "mdp1_mdp_fake_eng0", "ck2_mdp_ck", 16), + GATE_MDP10_V(CLK_MDP1_MDP_FAKE_ENG0_MML, "mdp1_mdp_fake_eng0_mml", "mdp1_mdp_fake_eng0"), + GATE_MDP10(CLK_MDP1_APB_DB, "mdp1_apb_db", "ck2_mdp_ck", 17), + GATE_MDP10_V(CLK_MDP1_APB_DB_MML, "mdp1_apb_db_mml", "mdp1_apb_db"), + GATE_MDP10(CLK_MDP1_MDP_DLI_ASYNC0, "mdp1_mdp_dli_async0", "ck2_mdp_ck", 18), + GATE_MDP10_V(CLK_MDP1_MDP_DLI_ASYNC0_MML, "mdp1_mdp_dli_async0_mml", "mdp1_mdp_dli_async0"), + GATE_MDP10(CLK_MDP1_MDP_DLI_ASYNC1, "mdp1_mdp_dli_async1", "ck2_mdp_ck", 19), + GATE_MDP10_V(CLK_MDP1_MDP_DLI_ASYNC1_MML, "mdp1_mdp_dli_async1_mml", "mdp1_mdp_dli_async1"), + GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC0, "mdp1_mdp_dlo_async0", "ck2_mdp_ck", 20), + GATE_MDP10_V(CLK_MDP1_MDP_DLO_ASYNC0_MML, "mdp1_mdp_dlo_async0_mml", "mdp1_mdp_dlo_async0"), + GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC1, "mdp1_mdp_dlo_async1", "ck2_mdp_ck", 21), + GATE_MDP10_V(CLK_MDP1_MDP_DLO_ASYNC1_MML, "mdp1_mdp_dlo_async1_mml", "mdp1_mdp_dlo_async1"), + GATE_MDP10(CLK_MDP1_MDP_DLI_ASYNC2, "mdp1_mdp_dli_async2", "ck2_mdp_ck", 22), + GATE_MDP10_V(CLK_MDP1_MDP_DLI_ASYNC2_MML, "mdp1_mdp_dli_async2_mml", "mdp1_mdp_dli_async2"), + GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC2, "mdp1_mdp_dlo_async2", "ck2_mdp_ck", 23), + GATE_MDP10_V(CLK_MDP1_MDP_DLO_ASYNC2_MML, "mdp1_mdp_dlo_async2_mml", "mdp1_mdp_dlo_async2"), + GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC3, "mdp1_mdp_dlo_async3", "ck2_mdp_ck", 24), + GATE_MDP10_V(CLK_MDP1_MDP_DLO_ASYNC3_MML, "mdp1_mdp_dlo_async3_mml", "mdp1_mdp_dlo_async3"), + GATE_MDP10(CLK_MDP1_IMG_DL_ASYNC0, "mdp1_img_dl_async0", "ck2_mdp_ck", 25), + GATE_MDP10_V(CLK_MDP1_IMG_DL_ASYNC0_MML, "mdp1_img_dl_async0_mml", "mdp1_img_dl_async0"), + GATE_MDP10(CLK_MDP1_MDP_RROT0, "mdp1_mdp_rrot0", "ck2_mdp_ck", 26), + GATE_MDP10_V(CLK_MDP1_MDP_RROT0_MML, "mdp1_mdp_rrot0_mml", "mdp1_mdp_rrot0"), + GATE_MDP10(CLK_MDP1_MDP_MERGE0, "mdp1_mdp_merge0", "ck2_mdp_ck", 27), + GATE_MDP10_V(CLK_MDP1_MDP_MERGE0_MML, "mdp1_mdp_merge0_mml", "mdp1_mdp_merge0"), + GATE_MDP10(CLK_MDP1_MDP_C3D0, "mdp1_mdp_c3d0", "ck2_mdp_ck", 28), + GATE_MDP10_V(CLK_MDP1_MDP_C3D0_MML, "mdp1_mdp_c3d0_mml", "mdp1_mdp_c3d0"), + GATE_MDP10(CLK_MDP1_MDP_FG0, "mdp1_mdp_fg0", "ck2_mdp_ck", 29), + GATE_MDP10_V(CLK_MDP1_MDP_FG0_MML, "mdp1_mdp_fg0_mml", "mdp1_mdp_fg0"), + GATE_MDP10(CLK_MDP1_MDP_CLA2, "mdp1_mdp_cla2", "ck2_mdp_ck", 30), + GATE_MDP10_V(CLK_MDP1_MDP_CLA2_MML, "mdp1_mdp_cla2_mml", "mdp1_mdp_cla2"), + GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC4, "mdp1_mdp_dlo_async4", "ck2_mdp_ck", 31), + GATE_MDP10_V(CLK_MDP1_MDP_DLO_ASYNC4_MML, "mdp1_mdp_dlo_async4_mml", "mdp1_mdp_dlo_async4"), + /* MDP11 */ + GATE_MDP11(CLK_MDP1_VPP_RSZ0, "mdp1_vpp_rsz0", "ck2_mdp_ck", 0), + GATE_MDP11_V(CLK_MDP1_VPP_RSZ0_MML, "mdp1_vpp_rsz0_mml", "mdp1_vpp_rsz0"), + GATE_MDP11(CLK_MDP1_VPP_RSZ1, "mdp1_vpp_rsz1", "ck2_mdp_ck", 1), + GATE_MDP11_V(CLK_MDP1_VPP_RSZ1_MML, "mdp1_vpp_rsz1_mml", "mdp1_vpp_rsz1"), + GATE_MDP11(CLK_MDP1_MDP_DLO_ASYNC5, "mdp1_mdp_dlo_async5", "ck2_mdp_ck", 2), + GATE_MDP11_V(CLK_MDP1_MDP_DLO_ASYNC5_MML, "mdp1_mdp_dlo_async5_mml", "mdp1_mdp_dlo_async5"), + GATE_MDP11(CLK_MDP1_IMG0, "mdp1_img0", "ck2_mdp_ck", 3), + GATE_MDP11_V(CLK_MDP1_IMG0_MML, "mdp1_img0_mml", "mdp1_img0"), + GATE_MDP11(CLK_MDP1_F26M, "mdp1_f26m", "ck_f26m_ck", 27), + GATE_MDP11_V(CLK_MDP1_F26M_MML, "mdp1_f26m_mml", "mdp1_f26m"), + /* MDP12 */ + GATE_MDP12(CLK_MDP1_IMG_DL_RELAY0, "mdp1_img_dl_relay0", "ck2_mdp_ck", 0), + GATE_MDP12_V(CLK_MDP1_IMG_DL_RELAY0_MML, "mdp1_img_dl_relay0_mml", "mdp1_img_dl_relay0"), + GATE_MDP12(CLK_MDP1_IMG_DL_RELAY1, "mdp1_img_dl_relay1", "ck2_mdp_ck", 8), + GATE_MDP12_V(CLK_MDP1_IMG_DL_RELAY1_MML, "mdp1_img_dl_relay1_mml", "mdp1_img_dl_relay1"), +}; + +static const struct mtk_clk_desc mdp1_mcd = { + .clks = mdp1_clks, + .num_clks = ARRAY_SIZE(mdp1_clks), + .need_runtime_pm = true, +}; + +static const struct mtk_gate_regs mdp0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs mdp1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +static const struct mtk_gate_regs mdp2_cg_regs = { + .set_ofs = 0x124, + .clr_ofs = 0x128, + .sta_ofs = 0x120, +}; + +#define GATE_MDP0(_id, _name, _parent, _shift) {\ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &mdp0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_OPS_PARENT_ENABLE, \ + .ops = &mtk_clk_gate_ops_setclr,\ + } + +#define GATE_MDP0_V(_id, _name, _parent) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &cg_regs_dummy, \ + .ops = &mtk_clk_dummy_ops, \ + } + +#define GATE_MDP1(_id, _name, _parent, _shift) {\ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &mdp1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_OPS_PARENT_ENABLE, \ + .ops = &mtk_clk_gate_ops_setclr,\ + } + +#define GATE_MDP1_V(_id, _name, _parent) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &cg_regs_dummy, \ + .ops = &mtk_clk_dummy_ops, \ + } + +#define GATE_MDP2(_id, _name, _parent, _shift) {\ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &mdp2_cg_regs, \ + .shift = _shift, \ + .flags = CLK_OPS_PARENT_ENABLE, \ + .ops = &mtk_clk_gate_ops_setclr,\ + } + +#define GATE_MDP2_V(_id, _name, _parent) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &cg_regs_dummy, \ + .ops = &mtk_clk_dummy_ops, \ + } + +static const struct mtk_gate mdp_clks[] = { + /* MDP0 */ + GATE_MDP0(CLK_MDP_MDP_MUTEX0, "mdp_mdp_mutex0", "ck2_mdp_ck", 0), + GATE_MDP0_V(CLK_MDP_MDP_MUTEX0_MML, "mdp_mdp_mutex0_mml", "mdp_mdp_mutex0"), + GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "ck2_mdp_ck", 1), + GATE_MDP0_V(CLK_MDP_SMI0_MML, "mdp_smi0_mml", "mdp_smi0"), + GATE_MDP0_V(CLK_MDP_SMI0_SMI, "mdp_smi0_smi", "mdp_smi0"), + GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "ck2_mdp_ck", 2), + GATE_MDP0_V(CLK_MDP_APB_BUS_MML, "mdp_apb_bus_mml", "mdp_apb_bus"), + GATE_MDP0(CLK_MDP_MDP_RDMA0, "mdp_mdp_rdma0", "ck2_mdp_ck", 3), + GATE_MDP0_V(CLK_MDP_MDP_RDMA0_MML, "mdp_mdp_rdma0_mml", "mdp_mdp_rdma0"), + GATE_MDP0(CLK_MDP_MDP_RDMA1, "mdp_mdp_rdma1", "ck2_mdp_ck", 4), + GATE_MDP0_V(CLK_MDP_MDP_RDMA1_MML, "mdp_mdp_rdma1_mml", "mdp_mdp_rdma1"), + GATE_MDP0(CLK_MDP_MDP_RDMA2, "mdp_mdp_rdma2", "ck2_mdp_ck", 5), + GATE_MDP0_V(CLK_MDP_MDP_RDMA2_MML, "mdp_mdp_rdma2_mml", "mdp_mdp_rdma2"), + GATE_MDP0(CLK_MDP_MDP_BIRSZ0, "mdp_mdp_birsz0", "ck2_mdp_ck", 6), + GATE_MDP0_V(CLK_MDP_MDP_BIRSZ0_MML, "mdp_mdp_birsz0_mml", "mdp_mdp_birsz0"), + GATE_MDP0(CLK_MDP_MDP_HDR0, "mdp_mdp_hdr0", "ck2_mdp_ck", 7), + GATE_MDP0_V(CLK_MDP_MDP_HDR0_MML, "mdp_mdp_hdr0_mml", "mdp_mdp_hdr0"), + GATE_MDP0(CLK_MDP_MDP_AAL0, "mdp_mdp_aal0", "ck2_mdp_ck", 8), + GATE_MDP0_V(CLK_MDP_MDP_AAL0_MML, "mdp_mdp_aal0_mml", "mdp_mdp_aal0"), + GATE_MDP0(CLK_MDP_MDP_RSZ0, "mdp_mdp_rsz0", "ck2_mdp_ck", 9), + GATE_MDP0_V(CLK_MDP_MDP_RSZ0_MML, "mdp_mdp_rsz0_mml", "mdp_mdp_rsz0"), + GATE_MDP0(CLK_MDP_MDP_RSZ2, "mdp_mdp_rsz2", "ck2_mdp_ck", 10), + GATE_MDP0_V(CLK_MDP_MDP_RSZ2_MML, "mdp_mdp_rsz2_mml", "mdp_mdp_rsz2"), + GATE_MDP0(CLK_MDP_MDP_TDSHP0, "mdp_mdp_tdshp0", "ck2_mdp_ck", 11), + GATE_MDP0_V(CLK_MDP_MDP_TDSHP0_MML, "mdp_mdp_tdshp0_mml", "mdp_mdp_tdshp0"), + GATE_MDP0(CLK_MDP_MDP_COLOR0, "mdp_mdp_color0", "ck2_mdp_ck", 12), + GATE_MDP0_V(CLK_MDP_MDP_COLOR0_MML, "mdp_mdp_color0_mml", "mdp_mdp_color0"), + GATE_MDP0(CLK_MDP_MDP_WROT0, "mdp_mdp_wrot0", "ck2_mdp_ck", 13), + GATE_MDP0_V(CLK_MDP_MDP_WROT0_MML, "mdp_mdp_wrot0_mml", "mdp_mdp_wrot0"), + GATE_MDP0(CLK_MDP_MDP_WROT1, "mdp_mdp_wrot1", "ck2_mdp_ck", 14), + GATE_MDP0_V(CLK_MDP_MDP_WROT1_MML, "mdp_mdp_wrot1_mml", "mdp_mdp_wrot1"), + GATE_MDP0(CLK_MDP_MDP_WROT2, "mdp_mdp_wrot2", "ck2_mdp_ck", 15), + GATE_MDP0_V(CLK_MDP_MDP_WROT2_MML, "mdp_mdp_wrot2_mml", "mdp_mdp_wrot2"), + GATE_MDP0(CLK_MDP_MDP_FAKE_ENG0, "mdp_mdp_fake_eng0", "ck2_mdp_ck", 16), + GATE_MDP0_V(CLK_MDP_MDP_FAKE_ENG0_MML, "mdp_mdp_fake_eng0_mml", "mdp_mdp_fake_eng0"), + GATE_MDP0(CLK_MDP_APB_DB, "mdp_apb_db", "ck2_mdp_ck", 17), + GATE_MDP0_V(CLK_MDP_APB_DB_MML, "mdp_apb_db_mml", "mdp_apb_db"), + GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC0, "mdp_mdp_dli_async0", "ck2_mdp_ck", 18), + GATE_MDP0_V(CLK_MDP_MDP_DLI_ASYNC0_MML, "mdp_mdp_dli_async0_mml", "mdp_mdp_dli_async0"), + GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC1, "mdp_mdp_dli_async1", "ck2_mdp_ck", 19), + GATE_MDP0_V(CLK_MDP_MDP_DLI_ASYNC1_MML, "mdp_mdp_dli_async1_mml", "mdp_mdp_dli_async1"), + GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC0, "mdp_mdp_dlo_async0", "ck2_mdp_ck", 20), + GATE_MDP0_V(CLK_MDP_MDP_DLO_ASYNC0_MML, "mdp_mdp_dlo_async0_mml", "mdp_mdp_dlo_async0"), + GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC1, "mdp_mdp_dlo_async1", "ck2_mdp_ck", 21), + GATE_MDP0_V(CLK_MDP_MDP_DLO_ASYNC1_MML, "mdp_mdp_dlo_async1_mml", "mdp_mdp_dlo_async1"), + GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC2, "mdp_mdp_dli_async2", "ck2_mdp_ck", 22), + GATE_MDP0_V(CLK_MDP_MDP_DLI_ASYNC2_MML, "mdp_mdp_dli_async2_mml", "mdp_mdp_dli_async2"), + GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC2, "mdp_mdp_dlo_async2", "ck2_mdp_ck", 23), + GATE_MDP0_V(CLK_MDP_MDP_DLO_ASYNC2_MML, "mdp_mdp_dlo_async2_mml", "mdp_mdp_dlo_async2"), + GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC3, "mdp_mdp_dlo_async3", "ck2_mdp_ck", 24), + GATE_MDP0_V(CLK_MDP_MDP_DLO_ASYNC3_MML, "mdp_mdp_dlo_async3_mml", "mdp_mdp_dlo_async3"), + GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "ck2_mdp_ck", 25), + GATE_MDP0_V(CLK_MDP_IMG_DL_ASYNC0_MML, "mdp_img_dl_async0_mml", "mdp_img_dl_async0"), + GATE_MDP0(CLK_MDP_MDP_RROT0, "mdp_mdp_rrot0", "ck2_mdp_ck", 26), + GATE_MDP0_V(CLK_MDP_MDP_RROT0_MML, "mdp_mdp_rrot0_mml", "mdp_mdp_rrot0"), + GATE_MDP0(CLK_MDP_MDP_MERGE0, "mdp_mdp_merge0", "ck2_mdp_ck", 27), + GATE_MDP0_V(CLK_MDP_MDP_MERGE0_MML, "mdp_mdp_merge0_mml", "mdp_mdp_merge0"), + GATE_MDP0(CLK_MDP_MDP_C3D0, "mdp_mdp_c3d0", "ck2_mdp_ck", 28), + GATE_MDP0_V(CLK_MDP_MDP_C3D0_MML, "mdp_mdp_c3d0_mml", "mdp_mdp_c3d0"), + GATE_MDP0(CLK_MDP_MDP_FG0, "mdp_mdp_fg0", "ck2_mdp_ck", 29), + GATE_MDP0_V(CLK_MDP_MDP_FG0_MML, "mdp_mdp_fg0_mml", "mdp_mdp_fg0"), + GATE_MDP0(CLK_MDP_MDP_CLA2, "mdp_mdp_cla2", "ck2_mdp_ck", 30), + GATE_MDP0_V(CLK_MDP_MDP_CLA2_MML, "mdp_mdp_cla2_mml", "mdp_mdp_cla2"), + GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC4, "mdp_mdp_dlo_async4", "ck2_mdp_ck", 31), + GATE_MDP0_V(CLK_MDP_MDP_DLO_ASYNC4_MML, "mdp_mdp_dlo_async4_mml", "mdp_mdp_dlo_async4"), + /* MDP1 */ + GATE_MDP1(CLK_MDP_VPP_RSZ0, "mdp_vpp_rsz0", "ck2_mdp_ck", 0), + GATE_MDP1_V(CLK_MDP_VPP_RSZ0_MML, "mdp_vpp_rsz0_mml", "mdp_vpp_rsz0"), + GATE_MDP1(CLK_MDP_VPP_RSZ1, "mdp_vpp_rsz1", "ck2_mdp_ck", 1), + GATE_MDP1_V(CLK_MDP_VPP_RSZ1_MML, "mdp_vpp_rsz1_mml", "mdp_vpp_rsz1"), + GATE_MDP1(CLK_MDP_MDP_DLO_ASYNC5, "mdp_mdp_dlo_async5", "ck2_mdp_ck", 2), + GATE_MDP1_V(CLK_MDP_MDP_DLO_ASYNC5_MML, "mdp_mdp_dlo_async5_mml", "mdp_mdp_dlo_async5"), + GATE_MDP1(CLK_MDP_IMG0, "mdp_img0", "ck2_mdp_ck", 3), + GATE_MDP1_V(CLK_MDP_IMG0_MML, "mdp_img0_mml", "mdp_img0"), + GATE_MDP1(CLK_MDP_F26M, "mdp_f26m", "ck_f26m_ck", 27), + GATE_MDP1_V(CLK_MDP_F26M_MML, "mdp_f26m_mml", "mdp_f26m"), + /* MDP2 */ + GATE_MDP2(CLK_MDP_IMG_DL_RELAY0, "mdp_img_dl_relay0", "ck2_mdp_ck", 0), + GATE_MDP2_V(CLK_MDP_IMG_DL_RELAY0_MML, "mdp_img_dl_relay0_mml", "mdp_img_dl_relay0"), + GATE_MDP2(CLK_MDP_IMG_DL_RELAY1, "mdp_img_dl_relay1", "ck2_mdp_ck", 8), + GATE_MDP2_V(CLK_MDP_IMG_DL_RELAY1_MML, "mdp_img_dl_relay1_mml", "mdp_img_dl_relay1"), +}; + +static const struct mtk_clk_desc mdp_mcd = { + .clks = mdp_clks, + .num_clks = ARRAY_SIZE(mdp_clks), + .need_runtime_pm = true, +}; + +static const struct of_device_id of_match_clk_mt8196_mdpsys[] = { + { .compatible = "mediatek,mt8196-mdpsys1", .data = &mdp1_mcd, }, + { .compatible = "mediatek,mt8196-mdpsys", .data = &mdp_mcd, }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8196_mdpsys_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8196-mdpsys", + .of_match_table = of_match_clk_mt8196_mdpsys, + }, +}; + +module_platform_driver(clk_mt8196_mdpsys_drv); +MODULE_LICENSE("GPL");

[16/26] clk: mediatek: Add MT8196 mdpsys clock support

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