@@ -273,6 +273,12 @@ const struct clk_ops mtk_clk_gate_ops_setclr = {
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr);
+const struct clk_ops mtk_clk_gate_ops_setclr_enable = {
+ .is_enabled = mtk_cg_bit_is_cleared,
+ .enable = mtk_cg_enable,
+};
+EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_enable);
+
const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
.is_enabled = mtk_cg_bit_is_set,
.enable = mtk_cg_enable_inv,
@@ -16,6 +16,7 @@ struct device;
struct device_node;
extern const struct clk_ops mtk_clk_gate_ops_setclr;
+extern const struct clk_ops mtk_clk_gate_ops_setclr_enable;
extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
Add gate ops without .disable and the ops is used for gate which is not allowed to disable but cannot affect its parent clock to disable. Signed-off-by: Guangjie Song <guangjie.song@mediatek.com> --- drivers/clk/mediatek/clk-gate.c | 6 ++++++ drivers/clk/mediatek/clk-gate.h | 1 + 2 files changed, 7 insertions(+)