From patchwork Fri Mar 7 03:44:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guangjie Song X-Patchwork-Id: 14005908 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E645BC282D0 for ; Fri, 7 Mar 2025 04:30:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=yjsKYsYt56CRuDyvJwITLsiWGxpc8ysryTjYQc7XD4Y=; b=Q08CG31GPBfUi62+qFKfDAEMK4 YzlqQRKqdRnFOnPSKreOfhtIaZikCPrMutfVOPoidfHKhmrHGDnaupHmtMKKlqEtGA21FKWs94Jm3 DhuSzKvx3ZVdhxlRIKsJLhHtMSGOK+a+AoIxvjjvPvph1o7cEV/Yn8HtYOl/8WxNnXNuDvKtsBywg JJMVLmnNdJLb25XUd/HSYHzIivEX7vYlqoUp92H/v2GYlR/YPUAgqovU3s3PcwH7vT5iLYsl/5689 a/zw341g/sW5aroiPgUS1ysX5rrj/7omtJrQymHTozQYT6YkZQekMRwDl4Vmy/sMPSzGK8S5t+0rU p6Vk1QTg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tqPLm-0000000D7Qm-2c21; Fri, 07 Mar 2025 04:30:18 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tqOe6-0000000D25D-0MEf; Fri, 07 Mar 2025 03:45:11 +0000 X-UUID: 8d583434fb0611efa1e849db4cc18d44-20250306 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=yjsKYsYt56CRuDyvJwITLsiWGxpc8ysryTjYQc7XD4Y=; b=R7UEm0WyQlTXPgEtvyPnho3NdpZqpICeZOF+UP4Fz0GCHn6jEGAnvoGdb/TllAGDDRblmE5BeETrKKXJgcwVT0qLlJ020bZAz+4zHjzdmd+GzH/VzIJxhFV4KiqIkI4mjRjXnh+yQHtJsO4cvnnpuqutcmcr5R8xW1/iF/u18U8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:e7954864-d2c8-424b-9c1a-4099239d6e64,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f,CLOUDID:af51cc49-a527-43d8-8af6-bc8b32d9f5e9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 8d583434fb0611efa1e849db4cc18d44-20250306 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 703057646; Thu, 06 Mar 2025 20:45:03 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Fri, 7 Mar 2025 11:45:01 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Fri, 7 Mar 2025 11:45:01 +0800 From: Guangjie Song To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson CC: , , , , , Guangjie Song , Subject: [PATCH 06/13] pmdomain: mediatek: Support trigger subsys save/restore regesters Date: Fri, 7 Mar 2025 11:44:30 +0800 Message-ID: <20250307034454.12243-7-guangjie.song@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250307034454.12243-1-guangjie.song@mediatek.com> References: <20250307034454.12243-1-guangjie.song@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250306_194510_143892_EF989157 X-CRM114-Status: GOOD ( 13.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Support trigger subsys save/restore registers during power domain on/off. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 106 ++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 1 deletion(-) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/mediatek/mtk-scpsys.c index df9cd012006c..0ae4c617b5a6 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -28,6 +28,7 @@ #define MTK_POLL_VOTE_PREPARE_CNT 2500 #define MTK_POLL_VOTE_PREPARE_US 2 #define MTK_ACK_DELAY_US 50 +#define MTK_RTFF_DELAY_US 10 #define MTK_STABLE_DELAY_US 100 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) @@ -37,6 +38,10 @@ #define MTK_SCPD_BYPASS_INIT_ON BIT(4) #define MTK_SCPD_IS_PWR_CON_ON BIT(5) #define MTK_SCPD_VOTE_OPS BIT(6) +#define MTK_SCPD_NON_CPU_RTFF BIT(7) +#define MTK_SCPD_PEXTP_PHY_RTFF BIT(8) +#define MTK_SCPD_UFS_RTFF BIT(9) +#define MTK_SCPD_RTFF_DELAY BIT(10) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 @@ -70,6 +75,11 @@ #define PWR_CLK_DIS_BIT BIT(4) #define PWR_SRAM_CLKISO_BIT BIT(5) #define PWR_SRAM_ISOINT_B_BIT BIT(6) +#define PWR_RTFF_SAVE BIT(24) +#define PWR_RTFF_NRESTORE BIT(25) +#define PWR_RTFF_CLK_DIS BIT(26) +#define PWR_RTFF_SAVE_FLAG BIT(27) +#define PWR_RTFF_UFS_CLK_DIS BIT(28) #define PWR_ACK BIT(30) #define PWR_ACK_2ND BIT(31) @@ -167,7 +177,7 @@ struct scp_domain_data { u32 sram_slp_ack_bits; u32 bus_prot_mask; enum clk_id clk_id[MAX_CLKS]; - u8 caps; + u32 caps; }; struct scp; @@ -179,6 +189,7 @@ struct scp_domain { const struct scp_domain_data *data; struct regulator *supply; struct regmap *vote_regmap; + bool rtff_flag; }; struct scp_ctrl_reg { @@ -428,15 +439,72 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) if (ret < 0) goto err_pwr_ack; + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_PEXTP_PHY_RTFF) && scpd->rtff_flag) { + val |= PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + } + val &= ~PWR_CLK_DIS_BIT; writel(val, ctl_addr); val &= ~PWR_ISO_BIT; writel(val, ctl_addr); + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_RTFF_DELAY) && scpd->rtff_flag) + udelay(MTK_RTFF_DELAY_US); + val |= PWR_RST_B_BIT; writel(val, ctl_addr); + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_NON_CPU_RTFF)) { + val = readl(ctl_addr); + if (val & PWR_RTFF_SAVE_FLAG) { + val &= ~PWR_RTFF_SAVE_FLAG; + writel(val, ctl_addr); + + val |= PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + + val &= ~PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val |= PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val &= ~PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + } + } else if (MTK_SCPD_CAPS(scpd, MTK_SCPD_PEXTP_PHY_RTFF)) { + val = readl(ctl_addr); + if (val & PWR_RTFF_SAVE_FLAG) { + val &= ~PWR_RTFF_SAVE_FLAG; + writel(val, ctl_addr); + + val &= ~PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val |= PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val &= ~PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + } + } else if (MTK_SCPD_CAPS(scpd, MTK_SCPD_UFS_RTFF) && scpd->rtff_flag) { + val |= PWR_RTFF_UFS_CLK_DIS; + writel(val, ctl_addr); + + val &= ~PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val |= PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val &= ~PWR_RTFF_UFS_CLK_DIS; + writel(val, ctl_addr); + + scpd->rtff_flag = false; + } + ret = scpsys_sram_enable(scpd, ctl_addr); if (ret < 0) goto err_pwr_ack; @@ -475,9 +543,45 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) /* subsys power off */ val = readl(ctl_addr); + + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_NON_CPU_RTFF) || + MTK_SCPD_CAPS(scpd, MTK_SCPD_PEXTP_PHY_RTFF)) { + val |= PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + + val |= PWR_RTFF_SAVE; + writel(val, ctl_addr); + + val &= ~PWR_RTFF_SAVE; + writel(val, ctl_addr); + + val &= ~PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + + val |= PWR_RTFF_SAVE_FLAG; + writel(val, ctl_addr); + } else if (MTK_SCPD_CAPS(scpd, MTK_SCPD_UFS_RTFF)) { + val |= PWR_RTFF_UFS_CLK_DIS; + writel(val, ctl_addr); + + val |= PWR_RTFF_SAVE; + writel(val, ctl_addr); + + val &= ~PWR_RTFF_SAVE; + writel(val, ctl_addr); + + val &= ~PWR_RTFF_UFS_CLK_DIS; + writel(val, ctl_addr); + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_UFS_RTFF)) + scpd->rtff_flag = true; + } + val |= PWR_ISO_BIT; writel(val, ctl_addr); + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_RTFF_DELAY) && scpd->rtff_flag) + udelay(1); + val &= ~PWR_RST_B_BIT; writel(val, ctl_addr);