[06/14] ASoC: mediatek: mt8196: support audio GPIO control

Message ID	20250307124841.23777-7-darren.ye@mediatek.com (mailing list archive)
State	New
Headers	show Return-Path: <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org> From: Darren.Ye <darren.ye@mediatek.com> To: Liam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>, Linus Walleij <linus.walleij@linaro.org>, Bartosz Golaszewski <brgl@bgdev.pl> CC: <linux-sound@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <linux-gpio@vger.kernel.org>, Darren Ye <darren.ye@mediatek.com> Subject: [PATCH 06/14] ASoC: mediatek: mt8196: support audio GPIO control Date: Fri, 7 Mar 2025 20:47:32 +0800 Message-ID: <20250307124841.23777-7-darren.ye@mediatek.com> In-Reply-To: <20250307124841.23777-1-darren.ye@mediatek.com> References: <20250307124841.23777-1-darren.ye@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
Series	ASoC: mediatek: Add support for MT8196 SoC \| expand [00/14] ASoC: mediatek: Add support for MT8196 SoC [01/14] ASoC: mediatek: common: modify mtk afe common driver for mt8196 [02/14] ASoC: mediatek: common: modify mtk afe platform driver for mt8196 [04/14] ASoC: mediatek: mt8196: add common interface for mt8196 DAI driver [05/14] ASoC: mediatek: mt8196: support audio clock control [06/14] ASoC: mediatek: mt8196: support audio GPIO control [07/14] ASoC: mediatek: mt8196: support ADDA in platform driver [09/14] ASoC: mediatek: mt8196: support TDM in platform driver [10/14] ASoC: mediatek: mt8196: support CM in platform driver [12/14] dt-bindings: mediatek: mt8196: add audio AFE document [13/14] ASoC: mediatek: mt8196: add machine driver with mt6681 [14/14] dt-bindings: mediatek: mt8196: add mt8196-mt6681 document

diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-gpio.c b/sound/soc/mediatek/mt8196/mt8196-afe-gpio.c new file mode 100644 index 000000000000..17ba409af7c4 --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-afe-gpio.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * mt8196-afe-gpio.c -- Mediatek 8196 afe gpio ctrl + * + * Copyright (c) 2024 MediaTek Inc. + * Author: Darren Ye <darren.ye@mediatek.com> + */ + +#include <linux/gpio.h> +#include <linux/pinctrl/consumer.h> + +#include "mt8196-afe-common.h" +#include "mt8196-afe-gpio.h" + +struct pinctrl *aud_pinctrl; +struct audio_gpio_attr { + const char *name; + bool gpio_prepare; + struct pinctrl_state *gpioctrl; +}; + +static struct audio_gpio_attr aud_gpios[MT8196_AFE_GPIO_GPIO_NUM] = { + [MT8196_AFE_GPIO_DAT_MISO0_OFF] = {"aud-dat-miso0-off", false, NULL}, + [MT8196_AFE_GPIO_DAT_MISO0_ON] = {"aud-dat-miso0-on", false, NULL}, + [MT8196_AFE_GPIO_DAT_MISO1_OFF] = {"aud-dat-miso1-off", false, NULL}, + [MT8196_AFE_GPIO_DAT_MISO1_ON] = {"aud-dat-miso1-on", false, NULL}, + [MT8196_AFE_GPIO_DAT_MOSI_OFF] = {"aud-dat-mosi-off", false, NULL}, + [MT8196_AFE_GPIO_DAT_MOSI_ON] = {"aud-dat-mosi-on", false, NULL}, + [MT8196_AFE_GPIO_I2SOUT0_OFF] = {"aud-gpio-i2sout0-off", false, NULL}, + [MT8196_AFE_GPIO_I2SOUT0_ON] = {"aud-gpio-i2sout0-on", false, NULL}, + [MT8196_AFE_GPIO_I2SIN0_OFF] = {"aud-gpio-i2sin0-off", false, NULL}, + [MT8196_AFE_GPIO_I2SIN0_ON] = {"aud-gpio-i2sin0-on", false, NULL}, + [MT8196_AFE_GPIO_I2SOUT1_OFF] = {"aud-gpio-i2sout1-off", false, NULL}, + [MT8196_AFE_GPIO_I2SOUT1_ON] = {"aud-gpio-i2sout1-on", false, NULL}, + [MT8196_AFE_GPIO_I2SIN1_OFF] = {"aud-gpio-i2sin1-off", false, NULL}, + [MT8196_AFE_GPIO_I2SIN1_ON] = {"aud-gpio-i2sin1-on", false, NULL}, + [MT8196_AFE_GPIO_I2SOUT4_OFF] = {"aud-gpio-i2sout4-off", false, NULL}, + [MT8196_AFE_GPIO_I2SOUT4_ON] = {"aud-gpio-i2sout4-on", false, NULL}, + [MT8196_AFE_GPIO_I2SIN4_OFF] = {"aud-gpio-i2sin4-off", false, NULL}, + [MT8196_AFE_GPIO_I2SIN4_ON] = {"aud-gpio-i2sin4-on", false, NULL}, + [MT8196_AFE_GPIO_I2SOUT6_OFF] = {"aud-gpio-i2sout6-off", false, NULL}, + [MT8196_AFE_GPIO_I2SOUT6_ON] = {"aud-gpio-i2sout6-on", false, NULL}, + [MT8196_AFE_GPIO_I2SIN6_OFF] = {"aud-gpio-i2sin6-off", false, NULL}, + [MT8196_AFE_GPIO_I2SIN6_ON] = {"aud-gpio-i2sin6-on", false, NULL}, + [MT8196_AFE_GPIO_AP_DMIC_OFF] = {"aud-gpio-ap-dmic-off", false, NULL}, + [MT8196_AFE_GPIO_AP_DMIC_ON] = {"aud-gpio-ap-dmic-on", false, NULL}, + [MT8196_AFE_GPIO_AP_DMIC1_OFF] = {"aud-gpio-ap-dmic1-off", false, NULL}, + [MT8196_AFE_GPIO_AP_DMIC1_ON] = {"aud-gpio-ap-dmic1-on", false, NULL}, + [MT8196_AFE_GPIO_DAT_MOSI_CH34_OFF] = {"aud-dat-mosi-ch34-off", false, NULL}, + [MT8196_AFE_GPIO_DAT_MOSI_CH34_ON] = {"aud-dat-mosi-ch34-on", false, NULL}, + [MT8196_AFE_GPIO_DAT_MISO_ONLY_OFF] = {"aud-dat-miso-only-off", false, NULL}, + [MT8196_AFE_GPIO_DAT_MISO_ONLY_ON] = {"aud-dat-miso-only-on", false, NULL}, + [MT8196_AFE_GPIO_I2SOUT3_OFF] = {"aud-gpio-i2sout3-off", false, NULL}, + [MT8196_AFE_GPIO_I2SOUT3_ON] = {"aud-gpio-i2sout3-on", false, NULL}, + [MT8196_AFE_GPIO_I2SIN3_OFF] = {"aud-gpio-i2sin3-off", false, NULL}, + [MT8196_AFE_GPIO_I2SIN3_ON] = {"aud-gpio-i2sin3-on", false, NULL}, +}; + +static DEFINE_MUTEX(gpio_request_mutex); + +int mt8196_afe_gpio_init(struct mtk_base_afe *afe) +{ + int ret; + int i = 0; + + aud_pinctrl = devm_pinctrl_get(afe->dev); + if (IS_ERR(aud_pinctrl)) { + ret = PTR_ERR(aud_pinctrl); + dev_info(afe->dev, "%s(), ret %d, cannot get aud_pinctrl!\n", + __func__, ret); + return -ENODEV; + } + + for (i = 0; i < MT8196_AFE_GPIO_GPIO_NUM; i++) { + if (!aud_gpios[i].name) { + dev_info(afe->dev, "%s(), gpio id %d not define!!!\n", + __func__, i); + } + } + + for (i = 0; i < ARRAY_SIZE(aud_gpios); i++) { + aud_gpios[i].gpioctrl = pinctrl_lookup_state(aud_pinctrl, + aud_gpios[i].name); + if (IS_ERR(aud_gpios[i].gpioctrl)) { + ret = PTR_ERR(aud_gpios[i].gpioctrl); + dev_info(afe->dev, "%s(), pinctrl_lookup_state %s fail, ret %d\n", + __func__, aud_gpios[i].name, ret); + } else { + aud_gpios[i].gpio_prepare = true; + } + } + + /* gpio status init */ + mt8196_afe_gpio_request(afe, false, MT8196_DAI_ADDA, 0); + mt8196_afe_gpio_request(afe, false, MT8196_DAI_ADDA, 1); + + return 0; +} + +static int mt8196_afe_gpio_select(struct mtk_base_afe *afe, + enum mt8196_afe_gpio type) +{ + int ret = 0; + + dev_dbg(afe->dev, "%s(), type: %d.\n", __func__, type); + + if (type >= MT8196_AFE_GPIO_GPIO_NUM) { + dev_info(afe->dev, "%s(), error, invalid gpio type %d\n", + __func__, type); + return -EINVAL; + } + + if (!aud_gpios[type].gpio_prepare) { + dev_info(afe->dev, "%s(), error, gpio type %d not prepared\n", + __func__, type); + return -EIO; + } + + ret = pinctrl_select_state(aud_pinctrl, + aud_gpios[type].gpioctrl); + if (ret) + dev_info(afe->dev, "%s(), error, can not set gpio type %d\n", + __func__, type); + + return ret; +} + +int mt8196_afe_gpio_request(struct mtk_base_afe *afe, bool enable, + int dai, int uplink) +{ + dev_dbg(afe->dev, "%s(), enable: %d, dai: %d, uplink: %d.\n", __func__, + enable, dai, uplink); + + mutex_lock(&gpio_request_mutex); + switch (dai) { + case MT8196_DAI_ADDA: + break; + case MT8196_DAI_ADDA_CH34: + break; + case MT8196_DAI_ADDA_CH56: + break; + case MT8196_DAI_I2S_IN0: + case MT8196_DAI_I2S_OUT0: + if (enable) { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SIN0_ON); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SOUT0_ON); + } else { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SIN0_OFF); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SOUT0_OFF); + } + break; + case MT8196_DAI_I2S_IN1: + case MT8196_DAI_I2S_OUT1: + if (enable) { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SIN1_ON); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SOUT1_ON); + } else { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SIN1_OFF); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SOUT1_OFF); + } + break; + case MT8196_DAI_I2S_IN3: + case MT8196_DAI_I2S_OUT3: + if (enable) { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SIN3_ON); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SOUT3_ON); + } else { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SIN3_OFF); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SOUT3_OFF); + } + break; + case MT8196_DAI_I2S_IN4: + case MT8196_DAI_I2S_OUT4: + if (enable) { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SIN4_ON); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SOUT4_ON); + } else { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SIN4_OFF); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SOUT4_OFF); + } + break; + case MT8196_DAI_I2S_IN6: + case MT8196_DAI_I2S_OUT6: + if (enable) { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SIN6_ON); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SOUT6_ON); + } else { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SIN6_OFF); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_I2SOUT6_OFF); + } + break; + case MT8196_DAI_VOW: + break; + case MT8196_DAI_VOW_SCP_DMIC: + break; + case MT8196_DAI_MTKAIF: + if (enable) { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_DAT_MISO1_ON); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_DAT_MISO0_ON); + } else { + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_DAT_MISO1_OFF); + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_DAT_MISO0_OFF); + } + break; + case MT8196_DAI_MISO_ONLY: + if (enable) + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_DAT_MISO_ONLY_ON); + else + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_DAT_MISO_ONLY_OFF); + break; + case MT8196_DAI_AP_DMIC: + if (enable) + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_AP_DMIC_ON); + else + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_AP_DMIC_OFF); + break; + case MT8196_DAI_AP_DMIC_CH34: + if (enable) + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_AP_DMIC1_ON); + else + mt8196_afe_gpio_select(afe, MT8196_AFE_GPIO_AP_DMIC1_OFF); + break; + default: + mutex_unlock(&gpio_request_mutex); + dev_info(afe->dev, "%s(), invalid dai %d\n", __func__, dai); + return -EINVAL; + } + mutex_unlock(&gpio_request_mutex); + + return 0; +} +EXPORT_SYMBOL_GPL(mt8196_afe_gpio_request); + +bool mt8196_afe_gpio_is_prepared(enum mt8196_afe_gpio type) +{ + return aud_gpios[type].gpio_prepare; +} +EXPORT_SYMBOL(mt8196_afe_gpio_is_prepared); + diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-gpio.h b/sound/soc/mediatek/mt8196/mt8196-afe-gpio.h new file mode 100644 index 000000000000..b36a8201d649 --- /dev/null +++ b/sound/soc/mediatek/mt8196/mt8196-afe-gpio.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * mt8196-afe-gpio.h -- Mediatek 8196 afe gpio ctrl definition + * + * Copyright (c) 2023 MediaTek Inc. + * Author: Darren Ye <darren.ye@mediatek.com> + */ + +#ifndef _MT8196_AFE_GPIO_H_ +#define _MT8196_AFE_GPIO_H_ +#include "mt8196-afe-common.h" + +enum mt8196_afe_gpio { + MT8196_AFE_GPIO_DAT_MISO0_OFF, + MT8196_AFE_GPIO_DAT_MISO0_ON, + MT8196_AFE_GPIO_DAT_MISO1_OFF, + MT8196_AFE_GPIO_DAT_MISO1_ON, + MT8196_AFE_GPIO_DAT_MOSI_OFF, + MT8196_AFE_GPIO_DAT_MOSI_ON, + MT8196_AFE_GPIO_DAT_MOSI_CH34_OFF, + MT8196_AFE_GPIO_DAT_MOSI_CH34_ON, + MT8196_AFE_GPIO_DAT_MISO_ONLY_OFF, + MT8196_AFE_GPIO_DAT_MISO_ONLY_ON, + MT8196_AFE_GPIO_I2SIN0_OFF, + MT8196_AFE_GPIO_I2SIN0_ON, + MT8196_AFE_GPIO_I2SOUT0_OFF, + MT8196_AFE_GPIO_I2SOUT0_ON, + MT8196_AFE_GPIO_I2SIN1_OFF, + MT8196_AFE_GPIO_I2SIN1_ON, + MT8196_AFE_GPIO_I2SOUT1_OFF, + MT8196_AFE_GPIO_I2SOUT1_ON, + MT8196_AFE_GPIO_I2SIN4_OFF, + MT8196_AFE_GPIO_I2SIN4_ON, + MT8196_AFE_GPIO_I2SOUT4_OFF, + MT8196_AFE_GPIO_I2SOUT4_ON, + MT8196_AFE_GPIO_I2SIN6_OFF, + MT8196_AFE_GPIO_I2SIN6_ON, + MT8196_AFE_GPIO_I2SOUT6_OFF, + MT8196_AFE_GPIO_I2SOUT6_ON, + MT8196_AFE_GPIO_AP_DMIC_OFF, + MT8196_AFE_GPIO_AP_DMIC_ON, + MT8196_AFE_GPIO_AP_DMIC1_OFF, + MT8196_AFE_GPIO_AP_DMIC1_ON, + MT8196_AFE_GPIO_I2SIN3_OFF, + MT8196_AFE_GPIO_I2SIN3_ON, + MT8196_AFE_GPIO_I2SOUT3_OFF, + MT8196_AFE_GPIO_I2SOUT3_ON, + MT8196_AFE_GPIO_GPIO_NUM +}; + +struct mtk_base_afe; + +int mt8196_afe_gpio_init(struct mtk_base_afe *afe); +int mt8196_afe_gpio_request(struct mtk_base_afe *afe, bool enable, + int dai, int uplink); +bool mt8196_afe_gpio_is_prepared(enum mt8196_afe_gpio type); + +#endif

[06/14] ASoC: mediatek: mt8196: support audio GPIO control

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Patch