From patchwork Sat Mar 8 01:42:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 14007385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D510C282DE for ; Sat, 8 Mar 2025 01:55:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=M3jJd3tpX3la7lvYFrEWmDfyU53nCPlZfvukoqDcIKc=; b=vFeus+MVaxiZbjEl9ovts6SVQY EAnjFWfHbnCfmEQLDtEBKjBBPPeCzt8lNq1mmHTHUpDYkkUSjhjnVrkcfLewZW8vpWyfQHL8vX6gJ JHyw86+040t5rlSBC30+HtqgRpk9ZO/DyzTZ+kKANhLEdDS7sX2foGh1PnB+q/AOAI0Fs8kDOcGfp csTuhnbEudIKaCVJAIsogwy5jYS2oqz5tDFho6I85/TT0ZSXywtKHWYKE7LiCAshbZmmCmbkfcoVt 5ADDA7CKX/M/1U8X/AEQGgre9d7G1kd6+qidKK3LJe+/CEMNfX+eqGSJq1FzWERSg7MoFcyVu9Qhh Gc7yGhEA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tqjPn-0000000G1YD-1Qd9; Sat, 08 Mar 2025 01:55:47 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tqjDb-0000000G0F2-1xIo for linux-arm-kernel@lists.infradead.org; Sat, 08 Mar 2025 01:43:13 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id F41BD5C6388; Sat, 8 Mar 2025 01:40:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2C4D6C4CEE8; Sat, 8 Mar 2025 01:43:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741398190; bh=+1no2bmgs6MuDDaz2UkyIJNIWjs3RXM03IY6VUWb8zE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dBQvSLflLaX0+cE6PCQYAgRSjgZVW99IEjDuXjphaNyiiZPmVEtM68JizkrmxTbnA +FSURScp1Nrz+YZrIP+GTk/cvnIXMscezx+8Hvu7y90xpW0fpoHURz9Ol7YzCCVNYf UvG3eic8581Sf/1d/fMP4ygYoYE7CMC6oXcWYtT5veEUq6WTl2IAr8eip+wIG89QJm zjT9oln5pfuqBDQT/m4aTuH3+8NBVw5BGo94/AhRRFVeafGXO+bIQQLU2gjBHjuYqg bmQoioeVmQsdy29CUZJdxxBU+8Shd5D8mEoKxrUDbk3/leGNf+2KqOhWhSzUIguWmV 6nIwf09mCLwTg== From: Dmitry Baryshkov Date: Sat, 08 Mar 2025 03:42:25 +0200 Subject: [PATCH 07/10] drm/msm/dsi/phy: add configuration for SAR2130P MIME-Version: 1.0 Message-Id: <20250308-sar2130p-display-v1-7-1d4c30f43822@linaro.org> References: <20250308-sar2130p-display-v1-0-1d4c30f43822@linaro.org> In-Reply-To: <20250308-sar2130p-display-v1-0-1d4c30f43822@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3195; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=VXFGPbLULr+xGELX+USGVkfaqafdytyi08lrC/x1doQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBny6B/ItX1kvUroCr116lKASxD99TvaSse4Bc6b OlK1CfmWqKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ8ugfwAKCRCLPIo+Aiko 1aGuB/9WWobEdhqYrc0kUzYBH1t+pRRGWeXwjjU5ZodDktlzbj2G/O1unIpn/LiIVLU/o+sz9Yn Zieuv869flaCvYrE9vCtyKT5EHbsDo3xq2Nb4yygNo95NdRGKvMBD/vlAbZk4DyFWnqjtDMaCOD EjshhdDEW5TMJ8MeruMRmkpeRrfevKe/VnO/j0mk+IxlV8HmaPRvGjLhHGgdRY7FQxUjBtG3A4p C2KcCKUVeuQHJLaU07cwe7FGdIZZq9BBwxiWgI+CSNheaB1PnIowXvLtSo5Y/UMkOVbMmMnZyb5 HeqgrZu1iDzZruAi2jqYFAwH1r8ovgWcaf0J+DNi+MTJCJkF X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250307_174311_621908_BBA474CA X-CRM114-Status: GOOD ( 11.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Dmitry Baryshkov Qualcomm SAR2130P requires slightly different setup for the DSI PHY. It is a 5nm PHY (like SM8450), so supplies are the same, but the rest of the configuration is the same as SM8550 DSI PHY. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index c0bcc68289633fd7506ce4f1f963655d862e8f08..a58bafe9fe8635730cb82e8c82ec1ded394988cd 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -581,6 +581,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_7nm_cfgs }, { .compatible = "qcom,dsi-phy-7nm-8150", .data = &dsi_phy_7nm_8150_cfgs }, + { .compatible = "qcom,sar2130p-dsi-phy-5nm", + .data = &dsi_phy_5nm_sar2130p_cfgs }, { .compatible = "qcom,sc7280-dsi-phy-7nm", .data = &dsi_phy_7nm_7280_cfgs }, { .compatible = "qcom,sm6375-dsi-phy-7nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 1925418d9999a24263d6621299cae78f1fb9455c..1ed08b56e056094bc0096d07d4470b89d9824060 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index a92decbee5b5433853ed973747f7705d9079068d..cad55702746b8d35949d22090796cca60f03b9e1 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1289,6 +1289,29 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { .quirks = DSI_PHY_7NM_QUIRK_V4_3, }; +const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_97800uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae95000, 0xae97000 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V5_2, +}; + const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = { .has_phy_lane = true, .regulator_data = dsi_phy_7nm_98400uA_regulators,