From patchwork Mon Mar 10 13:10:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Coster X-Patchwork-Id: 14010125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 184D8C28B2E for ; Mon, 10 Mar 2025 14:46:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=E+tZKF179AKkkYoSZ3tNbtcGj8RLjxTmow/dGsw2X6o=; b=p5HtV3BP5gpAq/EXuerd4u4vYZ mCY+lMOu548mL9LheVHoYe1gFM7+Hw77sMFZprhiC0gx+vKImywAW4nKWjwF4UGo7ndjKSFJ1xPHe AVJhuu3GHqMIw4v519WiVNikUCLElN3F+tySXMJahkICkUc4IWPQ5hxZPkaGqfdiufxSMrhRUBa9B TY4tTHTNHyL2ciChrIBus7pb0AouuPIhiEzIkQxqMGHY0FJ+209XBXqXi0jUxiXW03Torx3azfNhC Kk4z5bcvG9B7e05k44owvsjlB/rw3k26gNa6JoQvCuWmC2X4DmRJQHk0yWTWxdO1vTAx91VakL9yV j+7S5STA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1treO7-00000002yRd-2p0z; Mon, 10 Mar 2025 14:45:51 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1trcuu-00000002k1S-0HrY for linux-arm-kernel@bombadil.infradead.org; Mon, 10 Mar 2025 13:11:36 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=CC:To:In-Reply-To:References: Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Sender:Reply-To:Content-ID:Content-Description; bh=E+tZKF179AKkkYoSZ3tNbtcGj8RLjxTmow/dGsw2X6o=; b=qhl6+gfWtEEL1gJ726BlQdDSDs DWwqMLslKfgpuZFcKi5YuiLqZlfQI3AGEU5DSy0EBCHSd4mpUlD3CrrR0aPPL9Fbz4IE7TJ80gZh6 yPchSVoCPoaLIVPu9A0jQ1d8ML7rGwUaI2pQtjSSMKskySDEVZaPdf8Ut/Hn30YmsTyOLLtrByDqM cMfNPhVJPaosHQ59JP30jJP7HpM7J7c3FCfzYXcDadQ78CxWRk0Oaxfoi53lTQzZL6sBMhRjvTZ1X tRnNMFfHzoVa+D1+z+z3GO2ZtkuB6lavstWTf1b11FMbdzxO5tEzvrm77Wc0MLMfydCZStQQe/2/c YAXpC9WA==; Received: from mx07-00376f01.pphosted.com ([185.132.180.163]) by desiato.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1trcue-00000001raC-28tI for linux-arm-kernel@lists.infradead.org; Mon, 10 Mar 2025 13:11:25 +0000 Received: from pps.filterd (m0168889.ppops.net [127.0.0.1]) by mx07-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52A55uUH006364; Mon, 10 Mar 2025 13:10:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=E +tZKF179AKkkYoSZ3tNbtcGj8RLjxTmow/dGsw2X6o=; b=m6EGmfhOgfS832gjQ J4I5nYmXAFsmSiDkjNzbbFFYcFV6EEkRlO93k3FTd4z7j9VQnikReQ+aLsz4wuV4 HcVxkbuZ0uFGTmsckHSL7hbutLO5wy9jZ5f+UjS+4Jx+IHxRRiJFkHgDJwT35UU8 x/EW3kQvwwWxazy9gJKtHAzXhIr3qkbFZqnoSfdsQekXGhYRkOrgJCyvVtZC/tFr AMmmY9HTnYu4MidrdVw5FG5iNJgw8c87uYFJjT9+UOD0h1Tn/rOpASZTzjMY0thA qgh5QE6tgUZJbexeNBWXopoqLKXzolntwy0p+Oy6BbNL47966RxpQDYeHQI0PeEa CF1DQ== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx07-00376f01.pphosted.com (PPS) with ESMTPS id 458ev09ery-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 10 Mar 2025 13:10:53 +0000 (GMT) Received: from Matts-MacBook-Pro.local (172.25.0.133) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 10 Mar 2025 13:10:52 +0000 From: Matt Coster Date: Mon, 10 Mar 2025 13:10:36 +0000 Subject: [PATCH v3 12/18] drm/imagination: Use callbacks for fw irq handling MIME-Version: 1.0 Message-ID: <20250310-sets-bxs-4-64-patch-v1-v3-12-143b3dbef02f@imgtec.com> References: <20250310-sets-bxs-4-64-patch-v1-v3-0-143b3dbef02f@imgtec.com> In-Reply-To: <20250310-sets-bxs-4-64-patch-v1-v3-0-143b3dbef02f@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge , "Alessio Belle" , Alexandru Dadu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6987; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=mVReQTYNxfBBMVHm+68qyzcU4c2E69FMe1VLR4/t4PY=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaSfe3JRaZbf5Cn+f1bNqI3dwfXrihNnnaBGqrll2zv92 WtiGvfJdpSyMIhxMMiKKbLsWGG5Qu2PmpbEjV/FMHNYmUCGMHBxCsBEHpQx/M+e2/6T/dDM2Od1 jnUzXibqe3b9ZvOvc7jP8cI0VenEspkM//Mfvlfik0rs2LxjBX+KeH1UyCdR9mkZDS+9DxvqFs4 6wgAA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-Originating-IP: [172.25.0.133] X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=CeII5Krl c=1 sm=1 tr=0 ts=67cee4dd cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=ETbM1kImDFEA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=6iF6CzAXET1p6JnpVhoA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: w2GSapEpbsB95Lfi5-cr3Bw2TAue3I4P X-Proofpoint-ORIG-GUID: w2GSapEpbsB95Lfi5-cr3Bw2TAue3I4P X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250310_131120_905913_F8ADAE5A X-CRM114-Status: GOOD ( 16.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This allows for more versatility in checking and clearing firmware registers used for interrupt handling. Signed-off-by: Matt Coster --- Changes in v3: - None - Link to v2: https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-14-3fd45d9fb0cf@imgtec.com Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-14-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_device.h | 18 +++++++++++++ drivers/gpu/drm/imagination/pvr_fw.h | 45 +++++++++---------------------- drivers/gpu/drm/imagination/pvr_fw_meta.c | 22 ++++++++++----- drivers/gpu/drm/imagination/pvr_fw_mips.c | 22 ++++++++++----- 4 files changed, 63 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h index 12bf0b9e5bfb48ef9e5ed9faa44e0896b7555f49..eb5da8c7040fc9e9751f433279cb0c92fd4d1336 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -739,4 +739,22 @@ pvr_ioctl_union_padding_check(void *instance, size_t union_offset, __union_size, __member_size); \ }) +/* + * These utility functions should more properly be placed in pvr_fw.h, but that + * would cause a dependency cycle between that header and this one. Since + * they're primarily used in pvr_device.c, let's put them in here for now. + */ + +static __always_inline bool +pvr_fw_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_dev->fw_dev.defs->irq_pending(pvr_dev); +} + +static __always_inline void +pvr_fw_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_dev->fw_dev.defs->irq_clear(pvr_dev); +} + #endif /* PVR_DEVICE_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h index 88ad713468ce3a1ee459b04dde5363c24791a4f1..ab69f40a7fbc6304171f16dd16d825a68b0362a5 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -167,29 +167,22 @@ struct pvr_fw_defs { int (*wrapper_init)(struct pvr_device *pvr_dev); /** - * @irq: FW Interrupt information. + * @irq_pending: Check interrupt status register for pending interrupts. * - * Those are processor dependent, and should be initialized by the - * processor backend in pvr_fw_funcs::init(). + * @pvr_dev: Target PowerVR device. + * + * This function is mandatory. */ - struct { - /** @status_reg: FW interrupt status register. */ - u32 status_reg; + bool (*irq_pending)(struct pvr_device *pvr_dev); - /** - * @clear_reg: FW interrupt clear register. - * - * If @status_reg == @clear_reg, we clear by write a bit to zero, - * otherwise we clear by writing a bit to one. - */ - u32 clear_reg; - - /** @status_mask: Bitmask of events to listen for in the status_reg. */ - u32 status_mask; - - /** @clear_mask: Value to write to the clear_reg in order to clear FW IRQs. */ - u32 clear_mask; - } irq; + /** + * @irq_clear: Clear pending interrupts. + * + * @pvr_dev: Target PowerVR device. + * + * This function is mandatory. + */ + void (*irq_clear)(struct pvr_device *pvr_dev); /** * @has_fixed_data_addr: Specify whether the firmware fixed data must be loaded at the @@ -390,18 +383,6 @@ struct pvr_fw_device { } fw_objs; }; -#define pvr_fw_irq_read_reg(pvr_dev, name) \ - pvr_cr_read32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg) - -#define pvr_fw_irq_write_reg(pvr_dev, name, value) \ - pvr_cr_write32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg, value) - -#define pvr_fw_irq_pending(pvr_dev) \ - (pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.status_mask) - -#define pvr_fw_irq_clear(pvr_dev) \ - pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_mask) - enum pvr_fw_processor_type { PVR_FW_PROCESSOR_TYPE_META = 0, PVR_FW_PROCESSOR_TYPE_MIPS, diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c index 4433b04e0adb3684b86a4e90f63d670a81ecd826..09de3a30b625013c190196e02074fe72d08629a6 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -531,6 +531,20 @@ pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj) fw_obj->fw_mm_node.size); } +static bool +pvr_meta_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS) & + ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN; +} + +static void +pvr_meta_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS, + ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK); +} + const struct pvr_fw_defs pvr_fw_defs_meta = { .init = pvr_meta_init, .fw_process = pvr_meta_fw_process, @@ -538,11 +552,7 @@ const struct pvr_fw_defs pvr_fw_defs_meta = { .vm_unmap = pvr_meta_vm_unmap, .get_fw_addr_with_offset = pvr_meta_get_fw_addr_with_offset, .wrapper_init = pvr_meta_wrapper_init, - .irq = { - .status_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, - .clear_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, - .status_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, - .clear_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, - }, + .irq_pending = pvr_meta_irq_pending, + .irq_clear = pvr_meta_irq_clear, .has_fixed_data_addr = false, }; diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/imagination/pvr_fw_mips.c index 2c3172841886b70eb7a9992ec3851f18adcad8d5..524a9bd0a20b64c509f5708cc61d93b4c864b835 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -227,6 +227,20 @@ pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset) ROGUE_FW_HEAP_MIPS_BASE; } +static bool +pvr_mips_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS) & + ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN; +} + +static void +pvr_mips_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, + ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN); +} + const struct pvr_fw_defs pvr_fw_defs_mips = { .init = pvr_mips_init, .fini = pvr_mips_fini, @@ -235,11 +249,7 @@ const struct pvr_fw_defs pvr_fw_defs_mips = { .vm_unmap = pvr_vm_mips_unmap, .get_fw_addr_with_offset = pvr_mips_get_fw_addr_with_offset, .wrapper_init = pvr_mips_wrapper_init, - .irq = { - .status_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, - .clear_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, - .status_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, - .clear_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN, - }, + .irq_pending = pvr_mips_irq_pending, + .irq_clear = pvr_mips_irq_clear, .has_fixed_data_addr = true, };