[v1,4/4] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device

Commit Message

Jie Gan March 10, 2025, 9:04 a.m. UTC

Add interrupts to enable byte-cntr function for TMC ETR devices.

Signed-off-by: Jie Gan <[e-mail]>
---
Dependency:
prerequisite-message-id: [e-mail]
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Krzysztof Kozlowski March 10, 2025, 9:08 a.m. UTC | #1

On 10/03/2025 10:04, Jie Gan wrote:
> Add interrupts to enable byte-cntr function for TMC ETR devices.
> 
> Signed-off-by: Jie Gan <[e-mail]>
> ---
> Dependency:
> prerequisite-message-id: [e-mail]
Which too generated such changelog? Why this cannot be lore link?

Best regards,
Krzysztof

Jie Gan March 10, 2025, 9:12 a.m. UTC | #2

On 3/10/2025 5:08 PM, Krzysztof Kozlowski wrote:
> On 10/03/2025 10:04, Jie Gan wrote:
>> Add interrupts to enable byte-cntr function for TMC ETR devices.
>>
>> Signed-off-by: Jie Gan <[e-mail]>
>> ---
>> Dependency:
>> prerequisite-message-id: [e-mail]
> Which too generated such changelog? Why this cannot be lore link?
> 
> Best regards,
> Krzysztof

Hi Krzysztof,

It was entered manually. It's my fault, will fix in next version.

Thanks,
Jie

Patch

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 93ca37843990..091ae73774fa 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -2425,6 +2425,11 @@  ctcu@4001000 {
 			clocks = <&aoss_qmp>;
 			clock-names = "apb";
 
+			interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "etr0",
+					  "etr1";
+
 			in-ports {
 				#address-cells = <1>;
 				#size-cells = <0>;