| Message ID | 20250311-imx-se-if-v13-3-9cc6d8fd6d1c@nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | v13: firmware: imx: driver for NXP secure-enclave | expand |
On Tue, Mar 11, 2025 at 09:09:34PM +0530, Pankaj Gupta wrote: > Add support for NXP secure enclave called EdgeLock Enclave > firmware (se-fw) for imx8ulp-evk. > > EdgeLock Enclave has a hardware limitation of restricted access to DDR > address: 0x80000000 to 0xAFFFFFFF, so reserve 1MB of DDR memory region > from 0x80000000. > > Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 17 ++++++++++++++++- > arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 13 +++++++++++-- > 2 files changed, 27 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts > index 290a49bea2f7..a25d71bf2c26 100644 > --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: (GPL-2.0+ OR MIT) > /* > - * Copyright 2021 NXP > + * Copyright 2021, 2025 NXP > */ > > /dts-v1/; > @@ -24,6 +24,17 @@ memory@80000000 { > device_type = "memory"; > reg = <0x0 0x80000000 0 0x80000000>; > }; space line here. > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + ele_reserved: ele-reserved@90000000 { > + compatible = "shared-dma-pool"; > + reg = <0 0x90000000 0 0x100000>; > + no-map; > + }; > + }; > > reserved-memory { > #address-cells = <2>; > @@ -259,6 +270,10 @@ &usdhc0 { > status = "okay"; > }; > > +&hsm0 { > + memory-region = <&ele_reserved>; > +}; > + > &fec { > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&pinctrl_enet>; > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > index 2562a35286c2..c79a5de227b3 100644 > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: (GPL-2.0+ OR MIT) > /* > - * Copyright 2021 NXP > + * Copyright 2021, 2025 NXP > */ > > #include <dt-bindings/clock/imx8ulp-clock.h> > @@ -154,7 +154,7 @@ sosc: clock-sosc { > #clock-cells = <0>; > }; > > - sram@2201f000 { > + sram0: sram@2201f000 { > compatible = "mmio-sram"; > reg = <0x0 0x2201f000 0x0 0x1000>; > > @@ -169,6 +169,8 @@ scmi_buf: scmi-sram-section@0 { > }; > > firmware { > + #address-cells = <1>; > + #size-cells = <0>; Needn't #address-cells and #size-cells because no regs in children nodes Frank > scmi { > compatible = "arm,scmi-smc"; > arm,smc-id = <0xc20000fe>; > @@ -186,6 +188,13 @@ scmi_sensor: protocol@15 { > #thermal-sensor-cells = <1>; > }; > }; > + > + hsm0: secure-enclave { > + compatible = "fsl,imx8ulp-se-ele-hsm"; > + mbox-names = "tx", "rx"; > + mboxes = <&s4muap 0 0>, <&s4muap 1 0>; > + sram = <&sram0>; > + }; > }; > > cm33: remoteproc-cm33 { > > -- > 2.43.0 >
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 290a49bea2f7..a25d71bf2c26 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2021 NXP + * Copyright 2021, 2025 NXP */ /dts-v1/; @@ -24,6 +24,17 @@ memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ele_reserved: ele-reserved@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x100000>; + no-map; + }; + }; reserved-memory { #address-cells = <2>; @@ -259,6 +270,10 @@ &usdhc0 { status = "okay"; }; +&hsm0 { + memory-region = <&ele_reserved>; +}; + &fec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_enet>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 2562a35286c2..c79a5de227b3 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2021 NXP + * Copyright 2021, 2025 NXP */ #include <dt-bindings/clock/imx8ulp-clock.h> @@ -154,7 +154,7 @@ sosc: clock-sosc { #clock-cells = <0>; }; - sram@2201f000 { + sram0: sram@2201f000 { compatible = "mmio-sram"; reg = <0x0 0x2201f000 0x0 0x1000>; @@ -169,6 +169,8 @@ scmi_buf: scmi-sram-section@0 { }; firmware { + #address-cells = <1>; + #size-cells = <0>; scmi { compatible = "arm,scmi-smc"; arm,smc-id = <0xc20000fe>; @@ -186,6 +188,13 @@ scmi_sensor: protocol@15 { #thermal-sensor-cells = <1>; }; }; + + hsm0: secure-enclave { + compatible = "fsl,imx8ulp-se-ele-hsm"; + mbox-names = "tx", "rx"; + mboxes = <&s4muap 0 0>, <&s4muap 1 0>; + sram = <&sram0>; + }; }; cm33: remoteproc-cm33 {
Add support for NXP secure enclave called EdgeLock Enclave firmware (se-fw) for imx8ulp-evk. EdgeLock Enclave has a hardware limitation of restricted access to DDR address: 0x80000000 to 0xAFFFFFFF, so reserve 1MB of DDR memory region from 0x80000000. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 17 ++++++++++++++++- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 13 +++++++++++-- 2 files changed, 27 insertions(+), 3 deletions(-)