| Message ID | 20250313-qcs615-v5-mm-cc-v6-6-ebf4b9a5e916@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for videocc, camcc, dispcc and gpucc on Qualcomm QCS615 platform | expand |
On Thu, Mar 13, 2025 at 12:29:43PM +0530, Taniya Das wrote: + > + '#reset-cells': > + const: 1 > + > + '#power-domain-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - '#clock-cells' > + - '#reset-cells' > + - '#power-domain-cells' > + I don't get why this binding is different than others and you do not reference qcom,gcc.yaml? Is it not applicable here? Other gpucc do reference. Best regards, Krzysztof
On 3/13/2025 1:54 PM, Krzysztof Kozlowski wrote: > On Thu, Mar 13, 2025 at 12:29:43PM +0530, Taniya Das wrote: > + >> + '#reset-cells': >> + const: 1 >> + >> + '#power-domain-cells': >> + const: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - '#clock-cells' >> + - '#reset-cells' >> + - '#power-domain-cells' >> + > > I don't get why this binding is different than others and you do not > reference qcom,gcc.yaml? Is it not applicable here? Other gpucc do > reference. > Yes, I will fix them and resend. > > Best regards, > Krzysztof >
On Thu, Mar 13, 2025 at 02:18:57PM +0530, Taniya Das wrote: > > > On 3/13/2025 1:54 PM, Krzysztof Kozlowski wrote: > > On Thu, Mar 13, 2025 at 12:29:43PM +0530, Taniya Das wrote: > > + > >> + '#reset-cells': > >> + const: 1 > >> + > >> + '#power-domain-cells': > >> + const: 1 > >> + > >> +required: > >> + - compatible > >> + - reg > >> + - clocks > >> + - '#clock-cells' > >> + - '#reset-cells' > >> + - '#power-domain-cells' > >> + > > > > I don't get why this binding is different than others and you do not > > reference qcom,gcc.yaml? Is it not applicable here? Other gpucc do > > reference. > > > > Yes, I will fix them and resend. > What is it that you will fix and resend? This patch or all other cases? Please stop just throwing stuff at the list and until something sticks, talk with the people who review your patches. Regards, Bjorn > > > > Best regards, > > Krzysztof > > >
diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..b798d2dd0f9cc0f0e742066c5da9a48cdc519243 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on QCS615 Qualcomm SoCs. + + See also: include/dt-bindings/clock/qcom,qcs615-gpucc.h + +properties: + compatible: + const: qcom,qcs615-gpucc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 GPUCC div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,qcs615-gcc.h> + + clock-controller@5090000 { + compatible = "qcom,qcs615-gpucc"; + reg = <0x5090000 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,qcs615-gpucc.h b/include/dt-bindings/clock/qcom,qcs615-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..6d8394b90d59074b93a26a9c027407a14b050b27 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs615-gpucc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H + +/* GPU_CC clocks */ +#define CRC_DIV_PLL0 0 +#define CRC_DIV_PLL1 1 +#define GPU_CC_PLL0 2 +#define GPU_CC_PLL1 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_GFX3D_CLK 5 +#define GPU_CC_CX_GFX3D_SLV_CLK 6 +#define GPU_CC_CX_GMU_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_GFX3D_CLK 12 +#define GPU_CC_GX_GFX3D_CLK_SRC 13 +#define GPU_CC_GX_GMU_CLK 14 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 15 +#define GPU_CC_SLEEP_CLK 16 + +/* GPU_CC power domains */ +#define CX_GDSC 0 +#define GX_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_CX_BCR 0 +#define GPU_CC_GFX3D_AON_BCR 1 +#define GPU_CC_GMU_BCR 2 +#define GPU_CC_GX_BCR 3 +#define GPU_CC_XO_BCR 4 + +#endif
Add DT bindings for the Graphics clock on QCS615 platforms. Add the relevant DT include definitions as well. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- .../bindings/clock/qcom,qcs615-gpucc.yaml | 66 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,qcs615-gpucc.h | 39 +++++++++++++ 2 files changed, 105 insertions(+)