| Message ID | 20250320122259.525613-1-parth105105@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] arm64: dts: ti: k3-j784s4-main: Enable ACSPCIE outputs for PCIe interfaces | expand |
On 13:22-20250320, Parth Pancholi wrote: > From: Parth Pancholi <parth.pancholi@toradex.com> > > TI J784S4-based devices, such as the AM69 SoC, provide PCIE_REFCLK outputs > from the SoC, which can be used to clock external PCIe endpoint devices. > Each PCIE_REFCLK output is enabled via the corresponding ACSPCIE clock buffer, > with each buffer supporting two PADs to provide reference clocks for two > associated PCIe instances. The mappings are as follows: > - PCIe0 -> ACSPCIE1 PAD0 > - PCIe1 -> ACSPCIE0 PAD0 > - PCIe2 -> ACSPCIE1 PAD1 > - PCIe3 -> ACSPCIE0 PAD1 > > This patch enables each ACSPCIE module and its corresponding PADs to ensure > that all PCIE_REFCLK outputs are functional. > > This change have been tested on an AM69-based custom hardware platform, > where all four PCIe instances (PCIe0, PCIe1, PCIe2, and PCIe3) with the > internal PCIE_REFCLK are utilized with various endpoint devices such as > a WiFi card, NVMe SSD, and PCIe-to-USB bridge. > > Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1484211/am69-pcie-refclk-out-and-acspcie-mappings > Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> > --- > This change depends on https://lore.kernel.org/all/20241209085157.1203168-1-s-vadapalli@ti.com/ > --- > .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 10 ++++++++-- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 10 ++++++---- > 2 files changed, 14 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > index 591609f3194c..854fdf7b771e 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > @@ -132,6 +132,11 @@ acspcie0_proxy_ctrl: clock-controller@1a090 { > compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; > reg = <0x1a090 0x4>; > }; > + > + acspcie1_proxy_ctrl: clock-controller@1a094 { > + compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; We have the same challenge with bindings as well? > + reg = <0x1a094 0x4>; > + }; > }; > > main_ehrpwm0: pwm@3000000 { > @@ -1067,11 +1072,12 @@ pcie0_rc: pcie@2900000 { > interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; > device_type = "pci"; > ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; > + ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x1>; > max-link-speed = <3>; > num-lanes = <4>; > power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; > - clocks = <&k3_clks 332 0>; > - clock-names = "fck"; > + clocks = <&k3_clks 332 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; > + clock-names = "fck", "pcie_refclk"; > #address-cells = <3>; > #size-cells = <2>; > bus-range = <0x0 0xff>; > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index 0160fe0da983..ebbc315649d0 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -34,8 +34,8 @@ pcie2_rc: pcie@2920000 { > max-link-speed = <3>; > num-lanes = <2>; > power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>; > - clocks = <&k3_clks 334 0>; > - clock-names = "fck"; > + clocks = <&k3_clks 334 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; > + clock-names = "fck", "pcie_refclk"; > #address-cells = <3>; > #size-cells = <2>; > bus-range = <0x0 0xff>; > @@ -45,6 +45,7 @@ pcie2_rc: pcie@2920000 { > dma-coherent; > dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; > ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; > + ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>; > status = "disabled"; > }; > > @@ -63,8 +64,8 @@ pcie3_rc: pcie@2930000 { > max-link-speed = <3>; > num-lanes = <2>; > power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>; > - clocks = <&k3_clks 335 0>; > - clock-names = "fck"; > + clocks = <&k3_clks 335 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; > + clock-names = "fck", "pcie_refclk"; > #address-cells = <3>; > #size-cells = <2>; > bus-range = <0x0 0xff>; > @@ -74,6 +75,7 @@ pcie3_rc: pcie@2930000 { > dma-coherent; > dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; > ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; > + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; > status = "disabled"; > }; > > -- > 2.34.1 >
On Thu, 2025-03-20 at 10:22 -0500, Nishanth Menon wrote: > On 13:22-20250320, Parth Pancholi wrote: > > From: Parth Pancholi <parth.pancholi@toradex.com> > > > > TI J784S4-based devices, such as the AM69 SoC, provide PCIE_REFCLK > > outputs > > from the SoC, which can be used to clock external PCIe endpoint > > devices. > > Each PCIE_REFCLK output is enabled via the corresponding ACSPCIE > > clock buffer, > > with each buffer supporting two PADs to provide reference clocks > > for two > > associated PCIe instances. The mappings are as follows: > > - PCIe0 -> ACSPCIE1 PAD0 > > - PCIe1 -> ACSPCIE0 PAD0 > > - PCIe2 -> ACSPCIE1 PAD1 > > - PCIe3 -> ACSPCIE0 PAD1 > > > > This patch enables each ACSPCIE module and its corresponding PADs > > to ensure > > that all PCIE_REFCLK outputs are functional. > > > > This change have been tested on an AM69-based custom hardware > > platform, > > where all four PCIe instances (PCIe0, PCIe1, PCIe2, and PCIe3) with > > the > > internal PCIE_REFCLK are utilized with various endpoint devices > > such as > > a WiFi card, NVMe SSD, and PCIe-to-USB bridge. > > > > Link: > > https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1484211/am69-pcie-refclk-out-and-acspcie-mappings > > Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> > > --- > > This change depends on > > https://lore.kernel.org/all/20241209085157.1203168-1-s-vadapalli@ti.com/ > > --- > > .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 10 > > ++++++++-- > > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 10 > > ++++++---- > > 2 files changed, 14 insertions(+), 6 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main- > > common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main- > > common.dtsi > > index 591609f3194c..854fdf7b771e 100644 > > --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > > @@ -132,6 +132,11 @@ acspcie0_proxy_ctrl: clock-controller@1a090 { > > compatible = "ti,j784s4-acspcie-proxy- > > ctrl", "syscon"; > > reg = <0x1a090 0x4>; > > }; > > + > > + acspcie1_proxy_ctrl: clock-controller@1a094 { > > + compatible = "ti,j784s4-acspcie-proxy- > > ctrl", "syscon"; > > We have the same challenge with bindings as well? I believe the binding challenges have been resolved. I tested on both 'ti-next' and 'next-20250320' with these two changes applied on top, and the DT checker did not report any issues. $ git log --oneline c1d1735f9bf1 (HEAD) arm64: dts: ti: k3-j784s4-main: Enable ACSPCIE outputs for PCIe interfaces 7cebddd4b6b3 arm64: dts: ti: k3-j784s4-j742s2-main-common: Enable ACSPCIE output for PCIe1 15b2ed044c78 (mainline_ti/ti-next, mainline_ti/HEAD, ti-next) Merge branch 'ti-k3-config-next' into ti-next $ make CHECK_DTBS=y ti/k3-am69-sk.dtb W=1 DTC [C] arch/arm64/boot/dts/ti/k3-am69-sk.dtb $ $ git log --oneline 04cf02fe8b01 (HEAD) arm64: dts: ti: k3-j784s4-main: Enable ACSPCIE outputs for PCIe interfaces ffccd1b771aa arm64: dts: ti: k3-j784s4-j742s2-main-common: Enable ACSPCIE output for PCIe1 73b8c1dbc250 (tag: next-20250320, linux_next/master) Add linux-next specific files for 20250320 $ make CHECK_DTBS=y ti/k3-am69-sk.dtb W=1 DTC [C] arch/arm64/boot/dts/ti/k3-am69-sk.dtb $ > > > + reg = <0x1a094 0x4>; > > + }; > > }; > > > > main_ehrpwm0: pwm@3000000 { > > @@ -1067,11 +1072,12 @@ pcie0_rc: pcie@2900000 { > > interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; > > device_type = "pci"; > > ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; > > + ti,syscon-acspcie-proxy-ctrl = > > <&acspcie1_proxy_ctrl 0x1>; > > max-link-speed = <3>; > > num-lanes = <4>; > > power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; > > - clocks = <&k3_clks 332 0>; > > - clock-names = "fck"; > > + clocks = <&k3_clks 332 0>, <&serdes1 > > CDNS_TORRENT_REFCLK_DRIVER>; > > + clock-names = "fck", "pcie_refclk"; > > #address-cells = <3>; > > #size-cells = <2>; > > bus-range = <0x0 0xff>; > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > > b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > > index 0160fe0da983..ebbc315649d0 100644 > > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > > @@ -34,8 +34,8 @@ pcie2_rc: pcie@2920000 { > > max-link-speed = <3>; > > num-lanes = <2>; > > power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>; > > - clocks = <&k3_clks 334 0>; > > - clock-names = "fck"; > > + clocks = <&k3_clks 334 0>, <&serdes1 > > CDNS_TORRENT_REFCLK_DRIVER>; > > + clock-names = "fck", "pcie_refclk"; > > #address-cells = <3>; > > #size-cells = <2>; > > bus-range = <0x0 0xff>; > > @@ -45,6 +45,7 @@ pcie2_rc: pcie@2920000 { > > dma-coherent; > > dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 > > 0x0>; > > ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; > > + ti,syscon-acspcie-proxy-ctrl = > > <&acspcie1_proxy_ctrl 0x3>; > > status = "disabled"; > > }; > > > > @@ -63,8 +64,8 @@ pcie3_rc: pcie@2930000 { > > max-link-speed = <3>; > > num-lanes = <2>; > > power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>; > > - clocks = <&k3_clks 335 0>; > > - clock-names = "fck"; > > + clocks = <&k3_clks 335 0>, <&serdes0 > > CDNS_TORRENT_REFCLK_DRIVER>; > > + clock-names = "fck", "pcie_refclk"; > > #address-cells = <3>; > > #size-cells = <2>; > > bus-range = <0x0 0xff>; > > @@ -74,6 +75,7 @@ pcie3_rc: pcie@2930000 { > > dma-coherent; > > dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 > > 0x0>; > > ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; > > + ti,syscon-acspcie-proxy-ctrl = > > <&acspcie0_proxy_ctrl 0x3>; > > status = "disabled"; > > }; > > > > -- > > 2.34.1 > > >
On Thu, Mar 20, 2025 at 01:22:59PM +0100, Parth Pancholi wrote: > From: Parth Pancholi <parth.pancholi@toradex.com> > > TI J784S4-based devices, such as the AM69 SoC, provide PCIE_REFCLK outputs > from the SoC, which can be used to clock external PCIe endpoint devices. > Each PCIE_REFCLK output is enabled via the corresponding ACSPCIE clock buffer, > with each buffer supporting two PADs to provide reference clocks for two > associated PCIe instances. The mappings are as follows: > - PCIe0 -> ACSPCIE1 PAD0 > - PCIe1 -> ACSPCIE0 PAD0 > - PCIe2 -> ACSPCIE1 PAD1 > - PCIe3 -> ACSPCIE0 PAD1 > > This patch enables each ACSPCIE module and its corresponding PADs to ensure > that all PCIE_REFCLK outputs are functional. > > This change have been tested on an AM69-based custom hardware platform, > where all four PCIe instances (PCIe0, PCIe1, PCIe2, and PCIe3) with the > internal PCIE_REFCLK are utilized with various endpoint devices such as > a WiFi card, NVMe SSD, and PCIe-to-USB bridge. > > Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1484211/am69-pcie-refclk-out-and-acspcie-mappings > Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> > --- > This change depends on https://lore.kernel.org/all/20241209085157.1203168-1-s-vadapalli@ti.com/ > --- > .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 10 ++++++++-- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 10 ++++++---- > 2 files changed, 14 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > index 591609f3194c..854fdf7b771e 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > @@ -132,6 +132,11 @@ acspcie0_proxy_ctrl: clock-controller@1a090 { > compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; > reg = <0x1a090 0x4>; > }; > + > + acspcie1_proxy_ctrl: clock-controller@1a094 { > + compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; > + reg = <0x1a094 0x4>; > + }; > }; > > main_ehrpwm0: pwm@3000000 { > @@ -1067,11 +1072,12 @@ pcie0_rc: pcie@2900000 { > interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; > device_type = "pci"; > ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; > + ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x1>; This should be set to 0x3 - Enable output from PAD0 and PAD1 of ACSPCIE1. Otherwise, we are depending on PCIe0 being probed before PCIe2. If PCIe0 is probed after PCIe2, it will result in: 1. PCIe2 => Writes 0x3 to ACSPCIE1 CTRL register since ti,syscon-acspcie-proxy-ctrl within pcie2_rc is 0x3 2. PCIe0 => Writes 0x1 to ACPSCIE1 CTRL register since ti,syscon-acspcie-proxy-ctrl within pcie0_rc is 0x1 As a result, ACSPCIE1 PAD1 required by PCIe2 will be disabled. To summarize, as done below for pcie2_rc and pcie3_rc, ti,syscon-acspcie-proxy-ctrl should be set to 0x3 at all places. > max-link-speed = <3>; > num-lanes = <4>; > power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; > - clocks = <&k3_clks 332 0>; > - clock-names = "fck"; > + clocks = <&k3_clks 332 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; > + clock-names = "fck", "pcie_refclk"; > #address-cells = <3>; > #size-cells = <2>; > bus-range = <0x0 0xff>; > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index 0160fe0da983..ebbc315649d0 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -34,8 +34,8 @@ pcie2_rc: pcie@2920000 { > max-link-speed = <3>; > num-lanes = <2>; > power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>; > - clocks = <&k3_clks 334 0>; > - clock-names = "fck"; > + clocks = <&k3_clks 334 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; > + clock-names = "fck", "pcie_refclk"; > #address-cells = <3>; > #size-cells = <2>; > bus-range = <0x0 0xff>; > @@ -45,6 +45,7 @@ pcie2_rc: pcie@2920000 { > dma-coherent; > dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; > ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; > + ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>; > status = "disabled"; > }; > > @@ -63,8 +64,8 @@ pcie3_rc: pcie@2930000 { > max-link-speed = <3>; > num-lanes = <2>; > power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>; > - clocks = <&k3_clks 335 0>; > - clock-names = "fck"; > + clocks = <&k3_clks 335 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; > + clock-names = "fck", "pcie_refclk"; > #address-cells = <3>; > #size-cells = <2>; > bus-range = <0x0 0xff>; > @@ -74,6 +75,7 @@ pcie3_rc: pcie@2930000 { > dma-coherent; > dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; > ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; > + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; > status = "disabled"; > }; Regards, Siddharth.
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 591609f3194c..854fdf7b771e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -132,6 +132,11 @@ acspcie0_proxy_ctrl: clock-controller@1a090 { compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; reg = <0x1a090 0x4>; }; + + acspcie1_proxy_ctrl: clock-controller@1a094 { + compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; + reg = <0x1a094 0x4>; + }; }; main_ehrpwm0: pwm@3000000 { @@ -1067,11 +1072,12 @@ pcie0_rc: pcie@2900000 { interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; + ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x1>; max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 332 0>; - clock-names = "fck"; + clocks = <&k3_clks 332 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 0160fe0da983..ebbc315649d0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -34,8 +34,8 @@ pcie2_rc: pcie@2920000 { max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 334 0>; - clock-names = "fck"; + clocks = <&k3_clks 334 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; @@ -45,6 +45,7 @@ pcie2_rc: pcie@2920000 { dma-coherent; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; + ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>; status = "disabled"; }; @@ -63,8 +64,8 @@ pcie3_rc: pcie@2930000 { max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 335 0>; - clock-names = "fck"; + clocks = <&k3_clks 335 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; @@ -74,6 +75,7 @@ pcie3_rc: pcie@2930000 { dma-coherent; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; status = "disabled"; };