| Message ID | 20250326063041.7126-2-crystal.guo@mediatek.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add an interface to get current DDR data rate | expand |
On Wed, Mar 26, 2025 at 02:30:31PM +0800, Crystal Guo wrote: > A MediaTek DRAM controller interface to provide the current DDR > data rate. > > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> > --- > .../memory-controllers/mediatek,dramc.yaml | 44 +++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml Where is the rest of the patchset in DT patchwork? Where is any changelog? Cover letter? What changed here? I receive dozen or hundreds of emails, so if you want to make it difficult for me to review, I will just ignore the patch. I mark it as changes requested. Best regards, Krzysztof
Il 26/03/25 08:56, Krzysztof Kozlowski ha scritto: > On Wed, Mar 26, 2025 at 02:30:31PM +0800, Crystal Guo wrote: >> A MediaTek DRAM controller interface to provide the current DDR >> data rate. >> >> Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> >> --- >> .../memory-controllers/mediatek,dramc.yaml | 44 +++++++++++++++++++ >> 1 file changed, 44 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml > > Where is the rest of the patchset in DT patchwork? Where is any > changelog? Cover letter? What changed here? > > I receive dozen or hundreds of emails, so if you want to make > it difficult for me to review, I will just ignore the patch. > > I mark it as changes requested. > Krzysztof, I do see that devicetree cc'ed in all of the patches that Crystal sent - including the cover letter... and the cover letter has a changelog... :-) Was there any temporary issue with the DT patchwork or something, maybe? I anyway had to request some changes so no worries. Cheers, Angelo
Il 26/03/25 07:30, Crystal Guo ha scritto: > A MediaTek DRAM controller interface to provide the current DDR > data rate. > > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> > --- > .../memory-controllers/mediatek,dramc.yaml | 44 +++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml > > diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml > new file mode 100644 > index 000000000000..8bdacfc36cb5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml The filename should be "mediatek,mt8196-dramc.yaml" > @@ -0,0 +1,44 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2025 MediaTek Inc. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek DRAM Controller (DRAMC) > + > +maintainers: > + - Crystal Guo <crystal.guo@mediatek.com> > + > +description: > + A MediaTek DRAM controller interface to provide the current data rate of DRAM. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8196-dramc P.S.: bindings maintainers: this driver is expected to get more compatibles soon. Cheers, Angelo > + > + reg: > + items: > + - description: anaphy registers > + - description: ddrphy registers > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + memory-controller@10236000 { > + compatible = "mediatek,mt8196-dramc"; > + reg = <0 0x10236000 0 0x2000>, > + <0 0x10238000 0 0x2000>; > + }; > + };
On 26/03/2025 11:17, AngeloGioacchino Del Regno wrote: > Il 26/03/25 08:56, Krzysztof Kozlowski ha scritto: >> On Wed, Mar 26, 2025 at 02:30:31PM +0800, Crystal Guo wrote: >>> A MediaTek DRAM controller interface to provide the current DDR >>> data rate. >>> >>> Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> >>> --- >>> .../memory-controllers/mediatek,dramc.yaml | 44 +++++++++++++++++++ >>> 1 file changed, 44 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml >> >> Where is the rest of the patchset in DT patchwork? Where is any >> changelog? Cover letter? What changed here? >> >> I receive dozen or hundreds of emails, so if you want to make >> it difficult for me to review, I will just ignore the patch. >> >> I mark it as changes requested. >> > > Krzysztof, I do see that devicetree cc'ed in all of the patches that Crystal > sent - including the cover letter... and the cover letter has a changelog... :-) > > Was there any temporary issue with the DT patchwork or something, maybe? > > I anyway had to request some changes so no worries. I was not precise. Rob's DT review process, which I also use, fetches entire thread with b4 and then runs local mail client (mutt) on it. I got only the binding patch. I see entire thread on my other mail client (I often don't connect these in my brain), so indeed no clue what happened. Best regards, Krzysztof
On Wed, 2025-03-26 at 11:18 +0100, AngeloGioacchino Del Regno wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > Il 26/03/25 07:30, Crystal Guo ha scritto: > > A MediaTek DRAM controller interface to provide the current DDR > > data rate. > > > > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> > > --- > > .../memory-controllers/mediatek,dramc.yaml | 44 > > +++++++++++++++++++ > > 1 file changed, 44 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/memory- > > controllers/mediatek,dramc.yaml > > > > diff --git a/Documentation/devicetree/bindings/memory- > > controllers/mediatek,dramc.yaml > > b/Documentation/devicetree/bindings/memory- > > controllers/mediatek,dramc.yaml > > new file mode 100644 > > index 000000000000..8bdacfc36cb5 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/memory- > > controllers/mediatek,dramc.yaml > > The filename should be "mediatek,mt8196-dramc.yaml" > For other MediaTek SOCs, the method of calculating current ddr data rate is similar to that of MT8196. After changing "mediatek,dramc.yaml" to "mediatek,mt8196-dramc.yaml", would future Mediatek SOCs need to add a separate yaml file again? or could they reuse mediatek,mt8196- dramc.yaml? Thank you for your guidance. Best regards, Crystal > > > @@ -0,0 +1,44 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +# Copyright (c) 2025 MediaTek Inc. > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml*__;Iw!!CTRNKA9wMg0ARbw!gH5hMTJ34ZcYfNMfLUNL-dH9SMyQGr06kJ4jij1anezByF7IBOSbkYNdqysgHoz-rSRNwM9r6RaaTC1MO2882ojif26oaBzg$ > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!gH5hMTJ34ZcYfNMfLUNL-dH9SMyQGr06kJ4jij1anezByF7IBOSbkYNdqysgHoz-rSRNwM9r6RaaTC1MO2882ojifw8f6sUH$ > > + > > +title: MediaTek DRAM Controller (DRAMC) > > + > > +maintainers: > > + - Crystal Guo <crystal.guo@mediatek.com> > > + > > +description: > > + A MediaTek DRAM controller interface to provide the current data > > rate of DRAM. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8196-dramc > > P.S.: bindings maintainers: this driver is expected to get more > compatibles soon. > > Cheers, > Angelo > > > > + > > + reg: > > + items: > > + - description: anaphy registers > > + - description: ddrphy registers > > + > > +additionalProperties: false > > + > > +required: > > + - compatible > > + - reg > > + > > +examples: > > + - | > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + memory-controller@10236000 { > > + compatible = "mediatek,mt8196-dramc"; > > + reg = <0 0x10236000 0 0x2000>, > > + <0 0x10238000 0 0x2000>; > > + }; > > + }; > >
Il 02/04/25 05:51, Crystal Guo (郭晶) ha scritto: > On Wed, 2025-03-26 at 11:18 +0100, AngeloGioacchino Del Regno wrote: >> External email : Please do not click links or open attachments until >> you have verified the sender or the content. >> >> >> Il 26/03/25 07:30, Crystal Guo ha scritto: >>> A MediaTek DRAM controller interface to provide the current DDR >>> data rate. >>> >>> Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> >>> --- >>> .../memory-controllers/mediatek,dramc.yaml | 44 >>> +++++++++++++++++++ >>> 1 file changed, 44 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/memory- >>> controllers/mediatek,dramc.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/memory- >>> controllers/mediatek,dramc.yaml >>> b/Documentation/devicetree/bindings/memory- >>> controllers/mediatek,dramc.yaml >>> new file mode 100644 >>> index 000000000000..8bdacfc36cb5 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/memory- >>> controllers/mediatek,dramc.yaml >> >> The filename should be "mediatek,mt8196-dramc.yaml" >> > > For other MediaTek SOCs, the method of calculating current ddr data > rate is similar to that of MT8196. After changing "mediatek,dramc.yaml" > to "mediatek,mt8196-dramc.yaml", would future Mediatek SOCs need to add > a separate yaml file again? or could they reuse mediatek,mt8196- > dramc.yaml? Thank you for your guidance. > Other MediaTek SoC will be able to reuse mediatek,mt8196-dramc.yaml if the hardware is similar. Cheers, Angelo > Best regards, > Crystal > >> >>> @@ -0,0 +1,44 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +# Copyright (c) 2025 MediaTek Inc. >>> +%YAML 1.2 >>> +--- >>> +$id: >>> https://urldefense.com/v3/__http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml*__;Iw!!CTRNKA9wMg0ARbw!gH5hMTJ34ZcYfNMfLUNL-dH9SMyQGr06kJ4jij1anezByF7IBOSbkYNdqysgHoz-rSRNwM9r6RaaTC1MO2882ojif26oaBzg$ >>> +$schema: >>> https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!gH5hMTJ34ZcYfNMfLUNL-dH9SMyQGr06kJ4jij1anezByF7IBOSbkYNdqysgHoz-rSRNwM9r6RaaTC1MO2882ojifw8f6sUH$ >>> + >>> +title: MediaTek DRAM Controller (DRAMC) >>> + >>> +maintainers: >>> + - Crystal Guo <crystal.guo@mediatek.com> >>> + >>> +description: >>> + A MediaTek DRAM controller interface to provide the current data >>> rate of DRAM. >>> + >>> +properties: >>> + compatible: >>> + items: >>> + - enum: >>> + - mediatek,mt8196-dramc >> >> P.S.: bindings maintainers: this driver is expected to get more >> compatibles soon. >> >> Cheers, >> Angelo >> >> >>> + >>> + reg: >>> + items: >>> + - description: anaphy registers >>> + - description: ddrphy registers >>> + >>> +additionalProperties: false >>> + >>> +required: >>> + - compatible >>> + - reg >>> + >>> +examples: >>> + - | >>> + soc { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + memory-controller@10236000 { >>> + compatible = "mediatek,mt8196-dramc"; >>> + reg = <0 0x10236000 0 0x2000>, >>> + <0 0x10238000 0 0x2000>; >>> + }; >>> + }; >> >>
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml new file mode 100644 index 000000000000..8bdacfc36cb5 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2025 MediaTek Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek DRAM Controller (DRAMC) + +maintainers: + - Crystal Guo <crystal.guo@mediatek.com> + +description: + A MediaTek DRAM controller interface to provide the current data rate of DRAM. + +properties: + compatible: + items: + - enum: + - mediatek,mt8196-dramc + + reg: + items: + - description: anaphy registers + - description: ddrphy registers + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + memory-controller@10236000 { + compatible = "mediatek,mt8196-dramc"; + reg = <0 0x10236000 0 0x2000>, + <0 0x10238000 0 0x2000>; + }; + };
A MediaTek DRAM controller interface to provide the current DDR data rate. Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> --- .../memory-controllers/mediatek,dramc.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml