From patchwork Thu Mar 27 11:27:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikolaos Pasaloukos X-Patchwork-Id: 14031071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 267A8C3600B for ; Thu, 27 Mar 2025 11:31:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:MIME-Version: Content-Transfer-Encoding:Content-ID:Content-Type:In-Reply-To:References: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6cRTMgWCkjOIFX2GGEP9rCAx3jwS3geaXAmiINUgP48=; b=ItBGK7I55DMtT9nBEz5UjPMFHW djQcZwMV7hREhMZm9HmhkhOTdeYujqlGnuAktpBDR5DluMwDF3jJ5tcsQYYPubFD9sq1OGzBaZ/9u lP/kJ27twcb4AZFr0H1lxPHn01RXJnVttta0xV9C4sc0ANcCEfkps6tw7oS1D9f0/rG97HbzjTtRC IVlXOhC2FpPD39iSww1+pGzm/Fmru4lkp4muAX1XY4GPUkkvbut9X8DRkvJ1gOnoWjLp5sSXyPjpB 9/y+xHEgWnF3DRG5s7UuP9vTzB/OA4gwopF15jcj7NRsaqpJn16keColrGlkE4bIxKSk5lbZ0XZ/o AIRgNWZQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.1 #2 (Red Hat Linux)) id 1txlS7-0000000ApRt-112g; Thu, 27 Mar 2025 11:31:15 +0000 Received: from mx07-0063e101.pphosted.com ([205.220.184.123]) by bombadil.infradead.org with esmtps (Exim 4.98.1 #2 (Red Hat Linux)) id 1txlOh-0000000Ap8I-3twH for linux-arm-kernel@lists.infradead.org; Thu, 27 Mar 2025 11:27:45 +0000 Received: from pps.filterd (m0247495.ppops.net [127.0.0.1]) by mx08-0063e101.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52RB3Ix5019756; Thu, 27 Mar 2025 11:27:23 GMT Received: from pnypr01cu001.outbound.protection.outlook.com (mail-centralindiaazlp17010007.outbound.protection.outlook.com [40.93.132.7]) by mx08-0063e101.pphosted.com (PPS) with ESMTPS id 45hkb2thc2-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Mar 2025 11:27:23 +0000 (GMT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=rNZ8PYbxHxE/kDQlaf3gn36R7gsR9JlxRsO2Fyc8gy2s1cNSaQFHSsVP9IWj+TFhGDp6tCUB4agXSLvEJp591TBOLML83ZULYQ8GXdA7SnpGOQzLreIXCtCKJ1NV7kCIsH1Y9xG/gPADw+YhcwViIxaGPNT7+Q819eGwQN8HYHsC9Qm/XknbJT8ei6zS5pmSs6qU1nCUt8mKpYVsjlYlWbtJErOOevuLtoNDqZcUkJ2l9t+QPDPFHI69Y6tdEBzy2pFxhYL3Qcc09XLT58wvkN9lAzglwjA8zJHHDRIp4OARoA8oJyO3vb3XvkKwSU3onnCeudC20eb6mYJUhOMF1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6cRTMgWCkjOIFX2GGEP9rCAx3jwS3geaXAmiINUgP48=; b=ZNmw5dGbJcuh3L7TIFI2DnFcadNUlphtLmyyh1H+MvDRYokDhrHoHVL6JNTkui48hcnvlPLLjStkdb5f8E9rDbutIhZzl5wVh3Bo+MPccNb/jpUuJVTdWWQ4THKO4JoiKmDs36JWtUFEd2jAXMusV7YtUbZ5ox80bAENPKjDmRj43ykvIQTMV2UPyKozlmeJicwU/nQcC5DB6c1vNhkP9AivOZM+zi61PLumC8aMRW6KRUmM8cEv/xmYW8yIzIAOXH2K0lYKqyrlYDXwMG2E6xhTvdKvXLIFGs3KjQ94H+F9RSVPgTxBdPUA9VQqhskMsVXMrmfdTvjMdTmxtT51kA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=blaize.com; dmarc=pass action=none header.from=blaize.com; dkim=pass header.d=blaize.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=BLAIZE.COM; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6cRTMgWCkjOIFX2GGEP9rCAx3jwS3geaXAmiINUgP48=; b=iWxcRQYwBxhnvNtNE6swQwJjv1Sm7WFajDphvAuGQI6qsmi7XGy9DS/SfI66MISkiUQUR/PjQdMXV4DGvdNOEoBIG7V1/lXZOoVlqM03cDpbCy9+2uEm3sYWRQxAMOYmiYH0xDnT4/tUuFV5xKeXCLNlN58uo6+0bDa7eQKTvZA= Received: from MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:12a::5) by MAZPR01MB8910.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:cd::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8534.44; Thu, 27 Mar 2025 11:27:05 +0000 Received: from MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM ([fe80::309a:12cf:74a4:5655]) by MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM ([fe80::309a:12cf:74a4:5655%4]) with mapi id 15.20.8583.026; Thu, 27 Mar 2025 11:27:05 +0000 From: Nikolaos Pasaloukos To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , James Cowgill , Matt Redfearn , Neil Jones , Linus Walleij , Bartosz Golaszewski , Matt Redfearn , Catalin Marinas , Will Deacon CC: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-gpio@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Nikolaos Pasaloukos Subject: [PATCH v2 2/3] gpio: Enable Blaize BLZP1600 GPIO support Thread-Topic: [PATCH v2 2/3] gpio: Enable Blaize BLZP1600 GPIO support Thread-Index: AQHbnwsqu974u+e5HE6WDS4ZvArPJw== Date: Thu, 27 Mar 2025 11:27:05 +0000 Message-ID: <20250327-kernel-upstreaming-add_gpio_support-v2-2-bbe51f8d66da@blaize.com> References: <20250327-kernel-upstreaming-add_gpio_support-v2-0-bbe51f8d66da@blaize.com> In-Reply-To: <20250327-kernel-upstreaming-add_gpio_support-v2-0-bbe51f8d66da@blaize.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MA0PR01MB10184:EE_|MAZPR01MB8910:EE_ x-ms-office365-filtering-correlation-id: 08662f9f-3587-4183-c289-08dd6d224d68 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|366016|1800799024|7416014|376014|38070700018|921020; x-microsoft-antispam-message-info: =?utf-8?q?ytMbMf0QSXkKVBvwB+xsBpVcxzHkKem?= =?utf-8?q?cwuxtOb5XtCdJcV6COrMIz8b6FuxoKlf3knPpJqG+0eepMSjjfPeh6oo88gY3eLQk?= =?utf-8?q?EORll1xPfgqv68KoYdD4bjBGoTsdiau0vUHi6waa/XJ4soizjbYlPezVbYrQRJpYQ?= =?utf-8?q?msGF81JwwHYWwLUiQG/2GCSPOUk42soHFJPECoT/2SXZ79TBfQ9rEr8MdX309gtaT?= =?utf-8?q?D4Fc7QXnc4xBA7p1nMNdJSq1U/nFfllZLINnjh3HQMmpQKF9N3zXYyefVi7iOcyk8?= =?utf-8?q?bLMoayeRNHflPjUUFIBRceCNVaOWJxQ5jLvb/e0cwxpVqtUbQZ9tmyiur3ZNreTsu?= =?utf-8?q?xnGAFprL8Bct8LCYO3mVadYzBYdgzpJJKwMByuWqt7lXqH7zzwYvNfjr03VbgtD/3?= =?utf-8?q?23vRQds5xsJ84ka+EReTgibCOzUoHQmrZeE1sapiEBm8H0sA7vgQaNteWk7S2LpPq?= =?utf-8?q?U22uuvaWUJH8XUsaEowm3up37zykwB4brUBZsqEnOD5tuwWin943i3f8oTRQLbHIt?= =?utf-8?q?cYX2xGVs/pZR0nDF8trWsVfDb75ZMw9Z36HGy78vWkKf+89rIy5sIfM/ntszdZlmk?= =?utf-8?q?PF6Gr/uOyT+fWI988BaqhauZp/GeoxzjL+5wADASf9QrBBHGFBcWmSzPHobj9Sh1D?= =?utf-8?q?V8uJcamn0CNI0KDudh1PlWWOLMIld+WXPdVmdefbckVvLienioMrM78DqsVISMGyd?= =?utf-8?q?6ghfJopj47k0K2b1hAqeKedkl3JOtTBwprXM/JNjLnk5dAS7NVRtWuvlxIA9zXb+u?= =?utf-8?q?LatBCWyNQqc2ee+SiFy6KhMrqbBbI0YZalhW8iSeRs0NOab0n0iO0EAWODTaGR1+p?= =?utf-8?q?oCRxUJWMsO8+AunkMsDKldsOxAXjlEcMtEy8Gal7DmmSbJ8ofr2pAV/9j7jLj8/Pf?= =?utf-8?q?zrD+i0BGpJ+b3f+vS7bEu36dC/U33b7j4QdxkRVNdcw6Nw8n0pQXDC0wonJcrUo41?= =?utf-8?q?dtugeT/6iFgBs3NMVatNqE2YOCwtMgOU0qWUd6vpjENOgDZTIONHz2VVTVDey69Wh?= =?utf-8?q?bYmRXX9GMSHAR3iZRh2NEVTRi/yZDEy7HaIu3hSrmGtVTk+EqB5QXLSdhErgVriZY?= =?utf-8?q?R3mgjvGEUdDI6ogEVHkoMXB2wQSloL6oXd8oSgeSzAYl7HUUuRGlf3OFVhTC3hf6l?= =?utf-8?q?W+JcdQxFPHUYKwc6G2YmEKDgyDyAIds/HjLIKZmu28+PfsK/t5b6zTYs38PidPfFy?= =?utf-8?q?ku4T6L63tpywqHvof51yzuJ/TYGgRdxhJWMqpEWbvtVFKZTwlYC5F3CcA/lSoFlgc?= =?utf-8?q?R9sU1DGr267ZeKgHNze8z452sr0GeieTfTgeu1Nfj9s5CNyEn2whVtgdQdXMXQo8j?= =?utf-8?q?3tkWcTw0tl6OW/7cFineAgcBwrNYMWKo5LY180VyGVjqnpZq4CM7cLkO1rvcP3rbM?= =?utf-8?q?rLB182rUMgB0tT1j0Xtp5z45wBEAZlUXw=3D=3D?= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(7416014)(376014)(38070700018)(921020);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?utf-8?q?vbYoWJoR3/kTCseGt389i34kloJD?= =?utf-8?q?AqCmf/iER4STnCGHOHOBMW2Tlb13D12xIumeHbAwSNCG/nqnGN0RRmA5PLKjCdHh8?= =?utf-8?q?9ueQ6FKJ7KwmmHSufggKt51G+MUmOXbL2oDblv3t+83oBQ5rcqNaHnbtlajI+nPsB?= =?utf-8?q?GrJr7lM3nPpdxrDrALJDVTMaXxsKyji/y0+KgwtmIEfzBLICgYeZSg3hRox0o+8CL?= =?utf-8?q?Ii57AN36fsW6qci+k/TW6prJpQVcdgQdr/ElyQnAbWCqKOlHKIj1EG0hv6lNr5FPK?= =?utf-8?q?iQ+BpgQEavya9Gmnc+CjClEw/x59GQ7ytmI8P7OVV7KNlUh3/ZMp7f9YH5Ug+U3h2?= =?utf-8?q?+I18v9cN/umNYqohZrl8NKz1JLUBfCwlNaHisrFuyJxSfyc44dHfOSeQRAiVZf/xu?= =?utf-8?q?hC5FGuz5O6avmhipfrdSn298iNrWgRzY+/b+jnZgwvHx1mdkD1RYIeffTBK4ogao4?= =?utf-8?q?sZfkByPqrCcLqfJ15HSYtHb4c/hm00Vt5sLe0+VdgkCEqvpzYk6t+VmEWTbDTCIy2?= =?utf-8?q?gsw2TdoRu3zvr1LZEqC774HagkZjcRPNxEP5n4nojEJoncHDtjUGL15pyUWwNSTUm?= =?utf-8?q?+jZejF7y4lMSxr5ZW77K1rFzmu74qhFku+I7yXBsLlL0hWABCr41NglQk1t3yAlWZ?= =?utf-8?q?3KBiTI+Hd3pesn/lQY/Xrxng2QQJkjsRwGR/ViPoEcrQ1N00EnLfc+Fi6aEdHj7um?= =?utf-8?q?rMro9m7+nb8hzLKOOAsrUAKDbnCEAm5DH+llNtnXDj0S3IG9fgjygiD+0lh2gvBBv?= =?utf-8?q?h+ko00dWrl70ttKsxFI1jR7uzR58AoY+/mJMfKaT2PRm18JIhK7dlVaBFKpT+rMqD?= =?utf-8?q?Phr8EuykQYHeXM0m//sP8t53SHX7a+uXo2k+KF5rvhIv7j+xWuMis0ZHl+69Jg2PL?= =?utf-8?q?851SfWgqNIXLoW7kOClMrlAKPv4nmCjEGuX2UNBp+Gn/0KYXZtaKbAEFN+ugGl/5M?= =?utf-8?q?xlCWM3RLHOBLi0YSMXx3KvES3HMnpq0qoHAEFcAaWPr2upxAzRsNe50TE1FxEZ46C?= =?utf-8?q?32sYNYZDSPP/fW8bb97rrlZDmsv4a7xtt8HmeGd6NdrPxPcQp8TzTgvQhBJCuGUSG?= =?utf-8?q?2n/DhGzyAEFKlRTUpeL9Lycf1IVUDt16IFRO9W8HovPXBUWPBXTzA7ZxZrpTe3dic?= =?utf-8?q?ghZnLF4zvw5TUR9Xysjqu5qcW6ed74OHT08IhwLH6bo1jjfO39WbxcrzvQrxlEQGI?= =?utf-8?q?X2HBMbXkfz/V6icBbVsx6/4BCJxhOEPXXuYMVKbbMfOClsdsfd1ulXRYy5xIze2Dr?= =?utf-8?q?qMRjiYqk2zf9nVJZ4ufFf3ljpOtzFhPEVuOtscpTGVDEpcOBElElnv7OglPn/vHVo?= =?utf-8?q?27/3iITwy4ihVZ8S057Q3+/5tS66RLQrI63dFioSpT78PbK9iJGkxe6dW75cJ7Ygj?= =?utf-8?q?6tu/LBRbtDIAbEG0NUGUs7r2B0goxkNUw+pfFZ3sZTVj8yqtV4dM9At/l5JbKzKYG?= =?utf-8?q?yQ4Pob0esMHa+YQExbznJZEVLCihzYfut1a3GVdfLqaBlyQDwU+7iqQdR51RPZ2Yg?= =?utf-8?q?saYK0exzquSyCQR2AwHoB1yvD9RIEFf3mg=3D=3D?= Content-ID: <10ECA4A5833D0B4F8387EA4815CDEA79@INDPRD01.PROD.OUTLOOK.COM> MIME-Version: 1.0 X-OriginatorOrg: blaize.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 08662f9f-3587-4183-c289-08dd6d224d68 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Mar 2025 11:27:05.1119 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 9d1c3c89-8615-4064-88a7-bb1a8537c779 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: A8eFMLPLMbgbB6lox8NjK9H1WlGh1w0YQf29rxAQ4p0VHMQprAX4Q5tZ2A6zDiABqXp48bBrvo5oe4SDjm0VX8T39OXWnyuVMbwwxrjYGdo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MAZPR01MB8910 X-Proofpoint-GUID: urTGtccJhigtMbyN4-JWgamc5xsBVmQS X-Proofpoint-ORIG-GUID: urTGtccJhigtMbyN4-JWgamc5xsBVmQS X-Authority-Analysis: v=2.4 cv=JvjxrN4C c=1 sm=1 tr=0 ts=67e5361b cx=c_pps a=5CkbgoO2JNAQOP1ij0Zt3g==:117 a=lCpzRmAYbLLaTzLvsPZ7Mbvzbb8=:19 a=wKuvFiaSGQ0qltdbU6+NXLB8nM8=:19 a=Ol13hO9ccFRV9qXi2t6ftBPywas=:19 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=H5OGdu5hBBwA:10 a=-5LYVjoNHPMA:10 a=KKAkSRfTAAAA:8 a=SrsycIMJAAAA:8 a=VwQbUJbxAAAA:8 a=2OjVGFKQAAAA:8 a=2SEOXymVjmBJmyg4i_4A:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=zapPnUM7SFj2ezx6rUw-:22 a=IYbNqeBGBecwsX3Swn6O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-27_01,2025-03-26_02,2024-11-22_01 X-Proofpoint-Spam-Reason: orgsafe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250327_042744_272903_A43DF65A X-CRM114-Status: GOOD ( 15.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Blaize BLZP1600 GPIO controller is provided by VeriSilicon Microelectronics based on the GPIO APB v0.2 design. It has 32 input/output ports which can be configured as edge or level triggered interrupts. It also provides a de-bounce feature. This controller is used on the Blaize BLZP1600 SoC. Reviewed-by: Linus Walleij Signed-off-by: Nikolaos Pasaloukos --- MAINTAINERS | 10 ++ drivers/gpio/Kconfig | 11 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-blzp1600.c | 283 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 305 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index eb75c95f6c455516f7b1c8b3a39ddded5b38e0a9..7890586c9f1a6ff4afe368b91924038e2433939f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4104,6 +4104,16 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.gi F: include/net/bluetooth/ F: net/bluetooth/ +BLZP1600 GPIO DRIVER +M: James Cowgill +M: Matt Redfearn +M: Neil Jones +M: Nikolaos Pasaloukos +L: linux-gpio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml +F: drivers/gpio/gpio-blzp1600.c + BONDING DRIVER M: Jay Vosburgh L: netdev@vger.kernel.org diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index add5ad29a673c09082a913cb2404073b2034af48..b893b071a8d2dc5df5e0cb15b1a41ad8e6cb2b23 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -213,6 +213,17 @@ config GPIO_BCM_XGS_IPROC help Say yes here to enable GPIO support for Broadcom XGS iProc SoCs. +config GPIO_BLZP1600 + tristate "Blaize BLZP1600 GPIO support" + default y if ARCH_BLAIZE + depends on OF_GPIO + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + help + Say Y or M here to add support for the Blaize BLZP1600 GPIO device. + The controller is based on the Verisilicon Microelectronics GPIO APB v0.2 + IP block. + config GPIO_BRCMSTB tristate "BRCMSTB GPIO support" default y if (ARCH_BRCMSTB || BMIPS_GENERIC) diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index af3ba4d81b583842893ea69e677fbe2abf31bc7b..a04de399af619921fff74b93820899960d1fe97f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o +obj-$(CONFIG_GPIO_BLZP1600) += gpio-blzp1600.o obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o obj-$(CONFIG_GPIO_CADENCE) += gpio-cadence.o diff --git a/drivers/gpio/gpio-blzp1600.c b/drivers/gpio/gpio-blzp1600.c new file mode 100644 index 0000000000000000000000000000000000000000..77ad0e596f3ea838cfdd46918847d35b5d66fdf5 --- /dev/null +++ b/drivers/gpio/gpio-blzp1600.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 VeriSilicon Limited. + * Copyright (C) 2025 Blaize, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_DIR_REG 0x00 +#define GPIO_CTRL_REG 0x04 +#define GPIO_SET_REG 0x08 +#define GPIO_CLR_REG 0x0C +#define GPIO_ODATA_REG 0x10 +#define GPIO_IDATA_REG 0x14 +#define GPIO_IEN_REG 0x18 +#define GPIO_IS_REG 0x1C +#define GPIO_IBE_REG 0x20 +#define GPIO_IEV_REG 0x24 +#define GPIO_RIS_REG 0x28 +#define GPIO_IM_REG 0x2C +#define GPIO_MIS_REG 0x30 +#define GPIO_IC_REG 0x34 +#define GPIO_DB_REG 0x38 +#define GPIO_DFG_REG 0x3C + +#define DRIVER_NAME "blzp1600-gpio" + +struct blzp1600_gpio { + void __iomem *base; + struct gpio_chip gc; + int irq; +}; + +static inline struct blzp1600_gpio *get_blzp1600_gpio_from_irq_data(struct irq_data *d) +{ + return gpiochip_get_data(irq_data_get_irq_chip_data(d)); +} + +static inline struct blzp1600_gpio *get_blzp1600_gpio_from_irq_desc(struct irq_desc *d) +{ + return gpiochip_get_data(irq_desc_get_handler_data(d)); +} + +static inline u32 blzp1600_gpio_read(struct blzp1600_gpio *chip, unsigned int offset) +{ + return readl_relaxed(chip->base + offset); +} + +static inline void blzp1600_gpio_write(struct blzp1600_gpio *chip, unsigned int offset, u32 val) +{ + writel_relaxed(val, chip->base + offset); +} + +static inline void blzp1600_gpio_rmw(void __iomem *reg, u32 mask, bool set) +{ + u32 val = readl_relaxed(reg); + + if (set) + val |= mask; + else + val &= ~mask; + + writel_relaxed(val, reg); +} + +static void blzp1600_gpio_irq_mask(struct irq_data *d) +{ + struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d); + + guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + blzp1600_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 1); +} + +static void blzp1600_gpio_irq_unmask(struct irq_data *d) +{ + struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d); + + guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + blzp1600_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 0); +} + +static void blzp1600_gpio_irq_ack(struct irq_data *d) +{ + struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d); + + blzp1600_gpio_write(chip, GPIO_IC_REG, BIT(d->hwirq)); +} + +static void blzp1600_gpio_irq_enable(struct irq_data *d) +{ + struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d); + + gpiochip_enable_irq(&chip->gc, irqd_to_hwirq(d)); + + guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + blzp1600_gpio_rmw(chip->base + GPIO_DIR_REG, BIT(d->hwirq), 0); + blzp1600_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 1); +} + +static void blzp1600_gpio_irq_disable(struct irq_data *d) +{ + struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d); + + guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + blzp1600_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 0); + gpiochip_disable_irq(&chip->gc, irqd_to_hwirq(d)); +} + +static int blzp1600_gpio_irq_set_type(struct irq_data *d, u32 type) +{ + struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d); + u32 edge_level, single_both, fall_rise; + int mask = BIT(d->hwirq); + + guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + edge_level = blzp1600_gpio_read(chip, GPIO_IS_REG); + single_both = blzp1600_gpio_read(chip, GPIO_IBE_REG); + fall_rise = blzp1600_gpio_read(chip, GPIO_IEV_REG); + + switch (type) { + case IRQ_TYPE_EDGE_BOTH: + edge_level &= ~mask; + single_both |= mask; + break; + case IRQ_TYPE_EDGE_RISING: + edge_level &= ~mask; + single_both &= ~mask; + fall_rise |= mask; + break; + case IRQ_TYPE_EDGE_FALLING: + edge_level &= ~mask; + single_both &= ~mask; + fall_rise &= ~mask; + break; + case IRQ_TYPE_LEVEL_HIGH: + edge_level |= mask; + fall_rise |= mask; + break; + case IRQ_TYPE_LEVEL_LOW: + edge_level |= mask; + fall_rise &= ~mask; + break; + default: + return -EINVAL; + } + + blzp1600_gpio_write(chip, GPIO_IS_REG, edge_level); + blzp1600_gpio_write(chip, GPIO_IBE_REG, single_both); + blzp1600_gpio_write(chip, GPIO_IEV_REG, fall_rise); + + if (type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(d, handle_level_irq); + else + irq_set_handler_locked(d, handle_edge_irq); + + return 0; +} + +static const struct irq_chip blzp1600_gpio_irqchip = { + .name = DRIVER_NAME, + .irq_ack = blzp1600_gpio_irq_ack, + .irq_mask = blzp1600_gpio_irq_mask, + .irq_unmask = blzp1600_gpio_irq_unmask, + .irq_set_type = blzp1600_gpio_irq_set_type, + .irq_enable = blzp1600_gpio_irq_enable, + .irq_disable = blzp1600_gpio_irq_disable, + .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static void blzp1600_gpio_irqhandler(struct irq_desc *desc) +{ + struct blzp1600_gpio *gpio = get_blzp1600_gpio_from_irq_desc(desc); + struct irq_chip *irqchip = irq_desc_get_chip(desc); + unsigned long irq_status; + int hwirq = 0; + + chained_irq_enter(irqchip, desc); + irq_status = blzp1600_gpio_read(gpio, GPIO_RIS_REG); + for_each_set_bit(hwirq, &irq_status, gpio->gc.ngpio) + generic_handle_domain_irq(gpio->gc.irq.domain, hwirq); + + chained_irq_exit(irqchip, desc); +} + +static int blzp1600_gpio_set_debounce(struct gpio_chip *gc, unsigned int offset, + unsigned int debounce) +{ + struct blzp1600_gpio *chip = gpiochip_get_data(gc); + + guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + blzp1600_gpio_rmw(chip->base + GPIO_DB_REG, BIT(offset), debounce); + + return 0; +} + +static int blzp1600_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config) +{ + u32 debounce; + + if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) + return -ENOTSUPP; + + debounce = pinconf_to_config_argument(config); + return blzp1600_gpio_set_debounce(gc, offset, debounce); +} + +static int blzp1600_gpio_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct blzp1600_gpio *chip; + struct gpio_chip *gc; + int ret; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(chip->base)) + return PTR_ERR(chip->base); + + ret = bgpio_init(&chip->gc, &pdev->dev, 4, chip->base + GPIO_IDATA_REG, + chip->base + GPIO_SET_REG, chip->base + GPIO_CLR_REG, + chip->base + GPIO_DIR_REG, NULL, 0); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to register generic gpio\n"); + + /* configure the gpio chip */ + gc = &chip->gc; + gc->set_config = blzp1600_gpio_set_config; + + if (of_property_read_bool(node, "interrupt-controller")) { + struct gpio_irq_chip *girq; + + chip->irq = platform_get_irq(pdev, 0); + if (chip->irq < 0) + return chip->irq; + + girq = &gc->irq; + gpio_irq_chip_set_chip(girq, &blzp1600_gpio_irqchip); + girq->parent_handler = blzp1600_gpio_irqhandler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + + girq->parents[0] = chip->irq; + girq->default_type = IRQ_TYPE_NONE; + } + + return devm_gpiochip_add_data(&pdev->dev, gc, chip); +} + +static const struct of_device_id blzp1600_gpio_of_match[] = { + { .compatible = "blaize,blzp1600-gpio", }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, blzp1600_gpio_of_match); + +static struct platform_driver blzp1600_gpio_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = of_match_ptr(blzp1600_gpio_of_match), + }, + .probe = blzp1600_gpio_probe, +}; + +module_platform_driver(blzp1600_gpio_driver); + +MODULE_AUTHOR("Nikolaos Pasaloukos "); +MODULE_DESCRIPTION("Blaize BLZP1600 GPIO driver"); +MODULE_LICENSE("GPL");