| Message ID | 20250328105822.3946767-1-jensenhuang@friendlyarm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: rockchip: Fix order of rockchip_pci_core_rsts | expand |
On Fri, Mar 28, 2025 at 06:58:22PM +0800, Jensen Huang wrote: > The order of rockchip_pci_core_rsts follows the previous comments suggesting > to avoid reordering. However, reset_control_bulk_deassert() applies resets in > reverse, which may lead to the link downgrading to 2.5 GT/s. > Oops! I failed to spot it... > This patch restores the deassert order and comments for core_rsts, introduced in > commit 58c6990c5ee7 ("PCI: rockchip: Improve the deassert sequence of four reset pins"). > > Tested on NanoPC-T4 with Samsung 970 Pro. > Thanks for the fix. > Fixes: 18715931a5c0 ("PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function") > Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani
在 2025/03/28 星期五 18:58, Jensen Huang 写道: > The order of rockchip_pci_core_rsts follows the previous comments suggesting > to avoid reordering. However, reset_control_bulk_deassert() applies resets in > reverse, which may lead to the link downgrading to 2.5 GT/s. > > This patch restores the deassert order and comments for core_rsts, introduced in > commit 58c6990c5ee7 ("PCI: rockchip: Improve the deassert sequence of four reset pins"). > > Tested on NanoPC-T4 with Samsung 970 Pro. Acked-by: Shawn Lin <shawn.lin@rock-chips.com> > > Fixes: 18715931a5c0 ("PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function") > Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com> > --- > drivers/pci/controller/pcie-rockchip.h | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h > index 11def598534b..4f63a03d535c 100644 > --- a/drivers/pci/controller/pcie-rockchip.h > +++ b/drivers/pci/controller/pcie-rockchip.h > @@ -320,11 +320,15 @@ static const char * const rockchip_pci_pm_rsts[] = { > "aclk", > }; > > +/* > + * Please don't reorder the deassert sequence of the following > + * four reset pins. > + */ > static const char * const rockchip_pci_core_rsts[] = { > - "mgmt-sticky", > - "core", > - "mgmt", > "pipe", > + "mgmt", > + "core", > + "mgmt-sticky", > }; > > struct rockchip_pcie {
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 11def598534b..4f63a03d535c 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -320,11 +320,15 @@ static const char * const rockchip_pci_pm_rsts[] = { "aclk", }; +/* + * Please don't reorder the deassert sequence of the following + * four reset pins. + */ static const char * const rockchip_pci_core_rsts[] = { - "mgmt-sticky", - "core", - "mgmt", "pipe", + "mgmt", + "core", + "mgmt-sticky", }; struct rockchip_pcie {
The order of rockchip_pci_core_rsts follows the previous comments suggesting to avoid reordering. However, reset_control_bulk_deassert() applies resets in reverse, which may lead to the link downgrading to 2.5 GT/s. This patch restores the deassert order and comments for core_rsts, introduced in commit 58c6990c5ee7 ("PCI: rockchip: Improve the deassert sequence of four reset pins"). Tested on NanoPC-T4 with Samsung 970 Pro. Fixes: 18715931a5c0 ("PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function") Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com> --- drivers/pci/controller/pcie-rockchip.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)