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Wed, 02 Apr 2025 08:17:44 -0700 (PDT) Received: from gpeter-l.roam.corp.google.com ([145.224.66.90]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b663860sm17469190f8f.39.2025.04.02.08.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Apr 2025 08:17:43 -0700 (PDT) From: Peter Griffin Date: Wed, 02 Apr 2025 16:17:33 +0100 Subject: [PATCH v6 4/4] pinctrl: samsung: Add filter selection support for alive bank on gs101 MIME-Version: 1.0 Message-Id: <20250402-pinctrl-fltcon-suspend-v6-4-78ce0d4eb30c@linaro.org> References: <20250402-pinctrl-fltcon-suspend-v6-0-78ce0d4eb30c@linaro.org> In-Reply-To: <20250402-pinctrl-fltcon-suspend-v6-0-78ce0d4eb30c@linaro.org> To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, kernel-team@android.com, jaewon02.kim@samsung.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250402_081745_789720_C301D7C6 X-CRM114-Status: GOOD ( 20.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Newer Exynos based SoCs have a filter selection bitfield in the filter configuration registers on alive bank pins. This allows the selection of a digital or analog delay filter for each pin. Add support for selecting and enabling the filter. On suspend we set the analog filter to all pins in the bank (as the digital filter relies on a clock). On resume the digital filter is reapplied to all pins in the bank. The digital filter is working via a clock and has an adjustable filter delay flt_width bitfield, whereas the analog filter uses a fixed delay. The filter determines to what extent signal fluctuations received through the pad are considered glitches. The code path can be exercised using echo mem > /sys/power/state And then wake the device using a eint gpio Reviewed-by: André Draszik Signed-off-by: Peter Griffin --- Changes since v2: * Ensure EXYNOS_FLTCON_DIGITAL bit is cleared (Andre) * Make it obvious that exynos_eint_set_filter() is conditional on bank type (Andre) Changes since v1: * Remove eint_flt_selectable bool as it can be deduced from EINT_TYPE_WKUP (Peter) * Move filter config comment to header (Andre) * Rename EXYNOS_FLTCON_DELAY to EXYNOS_FLTCON_ANALOG (Andre) * Remove misleading old comment (Andre) * Refactor exynos_eint_update_flt_reg() into a loop (Andre) Note: this patch was previously sent as part of the initial gs101/ Pixel 6 series and was dropped in v6. This new version incorporates the review feedback from Sam Protsenko here in v5. Link: https://lore.kernel.org/all/20231201160925.3136868-1-peter.griffin@linaro.org/T/#m79ced98939e895c840d812c8b4c2b3f33ce604c8 Changes since previous version * Drop fltcon_type enum and use bool eint_flt_selectable (Sam) * Refactor and add exynos_eint_update_flt_reg() (Sam) * Rename function to exynos_eint_set_filter() for easier readability (Sam) * Remove comments and `if bank->fltcon_type != FLT_DEFAULT)` checks and indentation (Sam) --- drivers/pinctrl/samsung/pinctrl-exynos.c | 34 ++++++++++++++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 20 +++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 0879684338c772e484174a94ac2c274cc7d932ed..f3e1c11abe55032ee4ed7eb4db861dbb1e60c2bf 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -370,6 +370,37 @@ struct exynos_eint_gpio_save { u32 eint_mask; }; +static void exynos_eint_update_flt_reg(void __iomem *reg, int cnt, int con) +{ + unsigned int val, shift; + int i; + + val = readl(reg); + for (i = 0; i < cnt; i++) { + shift = i * EXYNOS_FLTCON_LEN; + val &= ~(EXYNOS_FLTCON_DIGITAL << shift); + val |= con << shift; + } + writel(val, reg); +} + +/* + * Set the desired filter (digital or analog delay) and enable it to + * every pin in the bank. Note the filter selection bitfield is only + * found on alive banks. The filter determines to what extent signal + * fluctuations received through the pad are considered glitches. + */ +static void exynos_eint_set_filter(struct samsung_pin_bank *bank, int filter) +{ + unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->eint_fltcon_offset; + void __iomem *reg = bank->drvdata->virt_base + off; + unsigned int con = EXYNOS_FLTCON_EN | filter; + + for (int n = 0; n < bank->nr_pins; n += 4) + exynos_eint_update_flt_reg(reg + n, + min(bank->nr_pins - n, 4), con); +} + /* * exynos_eint_gpio_init() - setup handling of external gpio interrupts. * @d: driver data of samsung pinctrl driver. @@ -832,6 +863,7 @@ void gs101_pinctrl_suspend(struct samsung_pin_bank *bank) bank->name, save->eint_mask); } else if (bank->eint_type == EINT_TYPE_WKUP) { exynos_set_wakeup(bank); + exynos_eint_set_filter(bank, EXYNOS_FLTCON_ANALOG); } } @@ -887,6 +919,8 @@ void gs101_pinctrl_resume(struct samsung_pin_bank *bank) writel(save->eint_fltcon1, eint_fltcfg0 + 4); writel(save->eint_mask, regs + bank->irq_chip->eint_mask + bank->eint_offset); + } else if (bank->eint_type == EINT_TYPE_WKUP) { + exynos_eint_set_filter(bank, EXYNOS_FLTCON_DIGITAL); } } diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 2bee52b61b9317ff79c618c1dc53e98242805087..362dc533186fb4ab9926b38b8d34af07690f783d 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -52,6 +52,26 @@ #define EXYNOS_EINT_MAX_PER_BANK 8 #define EXYNOS_EINT_NR_WKUP_EINT +/* + * EINT filter configuration register (on alive banks) has + * the following layout. + * + * BitfieldName[PinNum][Bit:Bit] + * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24] + * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16] + * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8] + * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0] + * + * FLT_EN 0x0 = Disable, 0x1=Enable + * FLT_SEL 0x0 = Analog delay filter, 0x1 Digital filter (clock count) + * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1 + */ + +#define EXYNOS_FLTCON_EN BIT(7) +#define EXYNOS_FLTCON_DIGITAL BIT(6) +#define EXYNOS_FLTCON_ANALOG (0 << 6) +#define EXYNOS_FLTCON_LEN 8 + #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ { \ .type = &bank_type_off, \