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AJvYcCXDbaqrVwmfa5BD4egwJUNXvTtlR+lF0RDT8bOygoTSUC9W+lrelCWP66SY3L1lWqfIl844XjOm+PuqutxV587/@lists.infradead.org X-Gm-Message-State: AOJu0Yww8FWQy6zJ4AmQ8MJyYOiIrYTlJ8iFuC+p9MBy/+7sQww7EIJj aFSzJQpMQU5zXVNQ545pAFRx7ZdKuBMFU8uvl4irVTJm0f0Am/yE5AVKGg9K0oqOk9e2/KWRNkB 9 X-Google-Smtp-Source: AGHT+IF2odUx6KL5NWFPqm5G8r/6pPbHDFTjru8tv1QaI+AKSymC55lai62Y/Vh/TzF1U2eaSauiAA7d+M0= X-Received: from pjbpl10.prod.google.com ([2002:a17:90b:268a:b0:2fa:15aa:4d1e]) (user=yabinc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:538f:b0:2ea:8aac:6ac1 with SMTP id 98e67ed59e1d1-30572609c09mr225709a91.15.1743556781014; Tue, 01 Apr 2025 18:19:41 -0700 (PDT) Date: Tue, 1 Apr 2025 18:18:31 -0700 In-Reply-To: <20250402011832.2970072-1-yabinc@google.com> Mime-Version: 1.0 References: <20250402011832.2970072-1-yabinc@google.com> X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog Message-ID: <20250402011832.2970072-3-yabinc@google.com> Subject: [PATCH v2 2/3] coresight: catu: Prevent concurrent PERF and SYSFS mode enablement From: Yabin Cui To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yabin Cui , Leo Yan X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250401_181942_370962_556777CD X-CRM114-Status: GOOD ( 15.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A CATU device can be enabled for either PERF mode or SYSFS mode, but not both simultaneously. Consider the following race condition: CPU 1 enables CATU for PERF mode. CPU 2 enables CATU for SYSFS mode. It only increases refcnt. CPU 2 enables ETR for SYSFS mode. CPU 1 fails to enable ETR for PERF mode. This results in a CATU being enabled in PERF mode and an ETR enabled in SYSFS mode, leading to unknown behavior. To prevent this situation, this patch checks enabled mode of a CATU device before increasing its refcnt. Signed-off-by: Yabin Cui Suggested-by: James Clark Suggested-by: Leo Yan --- drivers/hwtracing/coresight/coresight-catu.c | 6 +++++- drivers/hwtracing/coresight/coresight-catu.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index b1d490dd7249..0caf3a3e75ce 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -466,7 +466,10 @@ static int catu_enable(struct coresight_device *csdev, enum cs_mode mode, CS_UNLOCK(catu_drvdata->base); rc = catu_enable_hw(catu_drvdata, mode, data); CS_LOCK(catu_drvdata->base); - } + if (!rc) + catu_drvdata->mode = mode; + } else if (catu_drvdata->mode != mode) + rc = -EBUSY; if (!rc) csdev->refcnt++; return rc; @@ -499,6 +502,7 @@ static int catu_disable(struct coresight_device *csdev, void *__unused) CS_UNLOCK(catu_drvdata->base); rc = catu_disable_hw(catu_drvdata); CS_LOCK(catu_drvdata->base); + catu_drvdata->mode = CS_MODE_DISABLED; } else { rc = -EBUSY; } diff --git a/drivers/hwtracing/coresight/coresight-catu.h b/drivers/hwtracing/coresight/coresight-catu.h index 755776cd19c5..ea406464f0a8 100644 --- a/drivers/hwtracing/coresight/coresight-catu.h +++ b/drivers/hwtracing/coresight/coresight-catu.h @@ -66,6 +66,7 @@ struct catu_drvdata { struct coresight_device *csdev; int irq; raw_spinlock_t spinlock; + enum cs_mode mode; }; #define CATU_REG32(name, offset) \