[v2,1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document optional aux clock

Commit Message

Marek Vasut April 6, 2025, 2:45 p.m. UTC

Document 'aux' clock which are used to supply the PCIe bus. This
is useful in case of a hardware setup, where the PCIe controller
input clock and the PCIe bus clock are supplied from the same
clock synthesiser, but from different differential clock outputs:

 ____________                    _____________
| R-Car PCIe |                  | PCIe device |
|            |                  |             |
|    PCIe RX<|==================|>PCIe TX     |
|    PCIe TX<|==================|>PCIe RX     |
|            |                  |             |
|   PCIe CLK<|======..  ..======|>PCIe CLK    |
'------------'      ||  ||      '-------------'
                    ||  ||
 ____________       ||  ||
|  9FGV0441  |      ||  ||
|            |      ||  ||
|   CLK DIF0<|======''  ||
|   CLK DIF1<|==========''
|   CLK DIF2<|
|   CLK DIF3<|
'------------'

The clock are named 'aux' because those are one of the clock listed in
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which
fit closest to the PCIe bus clock. According to that binding document,
the 'aux' clock describe clock which supply the PMC domain, which is
likely PCIe Mezzanine Card domain.

Tested-by: Niklas Söderlund <[e-mail]>
Signed-off-by: Marek Vasut <[e-mail]>
---
NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
      instead and add 'bus' clock outright ?
---
Cc: "Krzysztof Wilczyński" <[e-mail]>
Cc: "Rafał Miłecki" <[e-mail]>
Cc: Aradhya Bhatia <[e-mail]>
Cc: Bjorn Helgaas <[e-mail]>
Cc: Conor Dooley <[e-mail]>
Cc: Geert Uytterhoeven <[e-mail]>
Cc: Heiko Stuebner <[e-mail]>
Cc: Junhao Xie <[e-mail]>
Cc: Kever Yang <[e-mail]>
Cc: Krzysztof Kozlowski <[e-mail]>
Cc: Kuninori Morimoto <[e-mail]>
Cc: Lorenzo Pieralisi <[e-mail]>
Cc: Magnus Damm <[e-mail]>
Cc: Manivannan Sadhasivam <[e-mail]>
Cc: Neil Armstrong <[e-mail]>
Cc: Rob Herring <[e-mail]>
Cc: Yoshihiro Shimoda <[e-mail]>
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]
---
V2: - Add TB from Niklas
    - Document minItems in clock-names
---
 .../devicetree/bindings/pci/rcar-gen4-pci-host.yaml      | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Patch

diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
index bb3f843c59d91..528b916fdb99b 100644
--- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
@@ -46,12 +46,15 @@  properties:
       - const: app
 
   clocks:
-    maxItems: 2
+    minItems: 2
+    maxItems: 3
 
   clock-names:
+    minItems: 2
     items:
       - const: core
       - const: ref
+      - const: aux
 
   power-domains:
     maxItems: 1
@@ -105,8 +108,8 @@  examples:
                          <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
                          <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
             interrupt-names = "msi", "dma", "sft_ce", "app";
-            clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
-            clock-names = "core", "ref";
+            clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>, <&pcie0_clkgen>;
+            clock-names = "core", "ref", "aux";
             power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
             resets = <&cpg 624>;
             reset-names = "pwr";