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Sun, 06 Apr 2025 21:46:13 -0700 (PDT) From: Nick Chan Date: Mon, 07 Apr 2025 12:45:12 +0800 Subject: [PATCH v6 03/21] drivers/perf: apple_m1: Support per-implementation event tables MIME-Version: 1.0 Message-Id: <20250407-apple-cpmu-v6-3-ae8c2f225c1f@gmail.com> References: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> In-Reply-To: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5785; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=EJFsNO1IGYgWw/sW/3l8ohSThIK8Gp7CsvED/Dkp2Hc=; b=owEBbAKT/ZANAwAIAQHKCLemxQgkAcsmYgBn81iGKE0zEYSiAoOBhSC+TnTK7fNCFMRTYvM7Y 9EFozFfzcSJAjIEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ/NYhgAKCRABygi3psUI JOjAD/iZeh+v/hHQ9QkbyFUDYHTRNsZDJmI50M8KeuFjK+Y6Kiwxjd4JksnsOFWLiCPRTKEjW74 LQv84yH6xcHNytk0Rr50N7Ic/kYHlM08/AnELmDso63nC+/M7WghEjXc4711G/WSFQS2CNdCEqQ 52M4QbqSzPZhESod+ytQ1e6u3EBqcsyRX5RbywAvSSFli43aDjpyepPnQ049C1V2H8vu+dYPbCn vrR0W2oK0YMPvMiF7G/UpIcaUYjhu4nndMJZw8Bc77lCajsrEwvxUZ3Ta7UiGBxk2oY/lhgBU6p LRVoHMnuodVopxbkVgjqLZs1v1e/1zuwkH3m3NavJyu1nDCADhkD+PS/WxTYc21YJgwn7yJbcHn b9ti8RLpWHQhPrIDixgWmAgvFr0pKnw3QpLqJfRV3i4qv53nGEopgBxZcdEYnRjPfAVfjMqxyB0 PzKYWZJrA7HIal+h1tmCUDlWzM+HNsd4EGP600bAfrwavtiDq16Ckap/VttgU42730Fjm/ikBE3 Jtd/LQv32Ah4f9bVPmGUs0IL0w6pAiztFXzPMq/V3JqbwR3WeJD64tVX0kRwsejP/qfCXNtE6TA aljKH28PylFn4c5G8cdnvftd8pFVi96C1s9L7BIUZQD40ruC7u3FDTecGN3aJw8LSV5fphS8WEz UiBkOT9+dKfc3 X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214615_116225_06E5735D X-CRM114-Status: GOOD ( 17.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use per-implementation event tables to allow supporting implementations with a different list of events and event affinities. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 65 +++++++++++++++++++++++++---------------- 1 file changed, 40 insertions(+), 25 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index b800da3f7f61ffa972fcab5f24b42127f2c55ac6..d1bc850809993de044df8fd5d4dfc61341482ee7 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -43,9 +43,6 @@ * moment, we don't really need to distinguish between the two because we * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. - * - * If we eventually find out that the events are different across - * implementations, we'll have to introduce per cpu-type tables. */ enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, @@ -494,11 +491,12 @@ static void m1_pmu_write_counter(struct perf_event *event, u64 value) isb(); } -static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) +static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event, + const u16 event_affinities[M1_PMU_CFG_EVENT]) { unsigned long evtype = event->hw.config_base & M1_PMU_CFG_EVENT; - unsigned long affinity = m1_pmu_event_affinity[evtype]; + unsigned long affinity = event_affinities[evtype]; int idx; /* @@ -517,6 +515,12 @@ static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, return -EAGAIN; } +static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, m1_pmu_event_affinity); +} + static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -544,7 +548,8 @@ static void m1_pmu_stop(struct arm_pmu *cpu_pmu) __m1_pmu_set_mode(PMCR0_IMODE_OFF); } -static int m1_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_47(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* * Although the counters are 48bit wide, bit 47 is what @@ -552,18 +557,29 @@ static int m1_pmu_map_event(struct perf_event *event) * being 47bit wide to mimick the behaviour of the ARM PMU. */ event->hw.flags |= ARMPMU_EVT_47BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } -static int m2_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_63(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* - * Same deal as the above, except that M2 has 64bit counters. + * Same deal as the above, except with 64bit counters. * Which, as far as we're concerned, actually means 63 bits. * Yes, this is getting awkward. */ event->hw.flags |= ARMPMU_EVT_63BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); +} + +static int m1_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &m1_pmu_perf_map); +} + +static int m2_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_63(event, &m1_pmu_perf_map); } static int m1_pmu_map_pmuv3_event(unsigned int eventsel) @@ -624,25 +640,16 @@ static int m1_pmu_set_event_filter(struct hw_perf_event *event, return 0; } -static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags) +static int apple_pmu_init(struct arm_pmu *cpu_pmu) { cpu_pmu->handle_irq = m1_pmu_handle_irq; cpu_pmu->enable = m1_pmu_enable_event; cpu_pmu->disable = m1_pmu_disable_event; cpu_pmu->read_counter = m1_pmu_read_counter; cpu_pmu->write_counter = m1_pmu_write_counter; - cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->clear_event_idx = m1_pmu_clear_event_idx; cpu_pmu->start = m1_pmu_start; cpu_pmu->stop = m1_pmu_stop; - - if (flags & ARMPMU_EVT_47BIT) - cpu_pmu->map_event = m1_pmu_map_event; - else if (flags & ARMPMU_EVT_63BIT) - cpu_pmu->map_event = m2_pmu_map_event; - else - return WARN_ON(-EINVAL); - cpu_pmu->reset = m1_pmu_reset; cpu_pmu->set_event_filter = m1_pmu_set_event_filter; @@ -661,25 +668,33 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags) static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_firestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_avalanche_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_blizzard_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static const struct of_device_id m1_pmu_of_device_ids[] = {