| Message ID | 20250408-gicv5-host-v1-13-1f26db465f8d@kernel.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Arm GICv5: Host driver implementation | expand |
On Tue, Apr 8, 2025, at 12:50, Lorenzo Pieralisi wrote: > Add ICH_HFGWTR_EL2 register description to sysreg. > > Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> > Cc: Will Deacon <will@kernel.org> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Marc Zyngier <maz@kernel.org> No comment on the contents, but I feel that having ten patches adding new sysregs one group at a time is a bit worse than a single patch adding them all. The patch descriptions don't add any particular information about why these are distinct, and you need them all anyway, so I'd suggest combining them into a larger patch. Arnd
On Wed, Apr 09, 2025 at 09:48:49AM +0200, Arnd Bergmann wrote: > On Tue, Apr 8, 2025, at 12:50, Lorenzo Pieralisi wrote: > > Add ICH_HFGWTR_EL2 register description to sysreg. > > > > Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> > > Cc: Will Deacon <will@kernel.org> > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > Cc: Marc Zyngier <maz@kernel.org> > > No comment on the contents, but I feel that having ten patches > adding new sysregs one group at a time is a bit worse than a > single patch adding them all. The patch descriptions don't add > any particular information about why these are distinct, and you > need them all anyway, so I'd suggest combining them into a > larger patch. I posted them separately to simplify "reviewing" their content, I will do whatever is preferred. Thanks, Lorenzo
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0c0e805481c84a14ae62d199466171d97d54ef90..1b519e35000be328acfe26d51e098059f9cf9ef2 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3601,6 +3601,21 @@ Field 1 ICC_IDRn_EL1 Field 0 ICC_APR_EL1 EndSysreg +Sysreg ICH_HFGWTR_EL2 3 4 12 9 6 +Res0 63:21 +Field 20 ICC_PPI_ACTIVERn_EL1 +Field 19 ICC_PPI_PRIORITYRn_EL1 +Field 18 ICC_PPI_PENDRn_EL1 +Field 17 ICC_PPI_ENABLERn_EL1 +Res0 16:7 +Field 6 ICC_ICSR_EL1 +Field 5 ICC_PCR_EL1 +Res0 4:3 +Field 2 ICC_CR0_EL1 +Res0 1 +Field 0 ICC_APR_EL1 +EndSysreg + Sysreg ICH_HCR_EL2 3 4 12 11 0 Res0 63:32 Field 31:27 EOIcount
Add ICH_HFGWTR_EL2 register description to sysreg. Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <maz@kernel.org> --- arch/arm64/tools/sysreg | 15 +++++++++++++++ 1 file changed, 15 insertions(+)