| Message ID | 20250410013330.3609482-3-jie.gan@oss.qualcomm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | coresight: ctcu: Enable byte-cntr function for TMC ETR | expand |
On Thu, Apr 10, 2025 at 09:33:27AM GMT, Jie Gan wrote: > Add an interrupt property to CTCU device. The interrupt will be triggered > when the data size in the ETR buffer exceeds the threshlod of the typo: threshold? > BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register > of CTCU device will enable the interrupt. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 4/10/2025 2:47 PM, Krzysztof Kozlowski wrote: > On Thu, Apr 10, 2025 at 09:33:27AM GMT, Jie Gan wrote: >> Add an interrupt property to CTCU device. The interrupt will be triggered >> when the data size in the ETR buffer exceeds the threshlod of the > > typo: threshold? Will fix it in next version. Thanks, Jie > >> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register >> of CTCU device will enable the interrupt. > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Best regards, > Krzysztof > >
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index 843b52eaf872..ea05ad8f3dd3 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -39,6 +39,16 @@ properties: items: - const: apb + interrupts: + items: + - description: Byte cntr interrupt for etr0 + - description: Byte cntr interrupt for etr1 + + interrupt-names: + items: + - const: etr0 + - const: etr1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports @@ -56,6 +66,8 @@ additionalProperties: false examples: - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + ctcu@1001000 { compatible = "qcom,sa8775p-ctcu"; reg = <0x1001000 0x1000>; @@ -63,6 +75,11 @@ examples: clocks = <&aoss_qmp>; clock-names = "apb"; + interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "etr0", + "etr1"; + in-ports { #address-cells = <1>; #size-cells = <0>;
Add an interrupt property to CTCU device. The interrupt will be triggered when the data size in the ETR buffer exceeds the threshlod of the BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register of CTCU device will enable the interrupt. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> --- .../bindings/arm/qcom,coresight-ctcu.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)