@@ -52,4 +52,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o
obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o
-coresight-ctcu-y := coresight-ctcu-core.o
+coresight-ctcu-y := coresight-ctcu-core.o coresight-ctcu-byte-cntr.o
new file mode 100644
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/coresight.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/of_irq.h>
+#include <linux/uaccess.h>
+
+#include "coresight-ctcu.h"
+#include "coresight-priv.h"
+#include "coresight-tmc.h"
+
+static irqreturn_t byte_cntr_handler(int irq, void *data)
+{
+ struct ctcu_byte_cntr *byte_cntr_data = (struct ctcu_byte_cntr *)data;
+
+ atomic_inc(&byte_cntr_data->irq_cnt);
+ wake_up(&byte_cntr_data->wq);
+
+ return IRQ_HANDLED;
+}
+
+/* Start the byte-cntr function when the path is enabled. */
+void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path)
+{
+ struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+ struct coresight_device *sink = coresight_get_sink(path);
+ struct ctcu_byte_cntr *byte_cntr_data;
+ struct tmc_drvdata *tmcdrvdata;
+ int port_num;
+
+ if (!sink)
+ return;
+
+ tmcdrvdata = dev_get_drvdata(sink->dev.parent);
+ port_num = ctcu_get_active_port(sink, csdev);
+ if (port_num < 0)
+ return;
+
+ byte_cntr_data = &drvdata->byte_cntr_data[port_num];
+ /* Don't start byte-cntr function when threshold is not set. */
+ if (!byte_cntr_data->thresh_val)
+ return;
+
+ guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock);
+ atomic_set(&byte_cntr_data->irq_cnt, 0);
+ tmcdrvdata->byte_cntr_data = byte_cntr_data;
+ byte_cntr_data->enable = true;
+}
+
+/* Stop the byte-cntr function when the path is disabled. */
+void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path)
+{
+ struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+ struct coresight_device *sink = coresight_get_sink(path);
+ struct ctcu_byte_cntr *byte_cntr_data;
+ struct tmc_drvdata *tmcdrvdata;
+ long w_offset;
+ int port_num;
+
+ if (!sink)
+ return;
+
+ port_num = ctcu_get_active_port(sink, csdev);
+ if (port_num < 0)
+ return;
+
+ byte_cntr_data = &drvdata->byte_cntr_data[port_num];
+ tmcdrvdata = dev_get_drvdata(sink->dev.parent);
+
+ guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock);
+ /* Store the w_offset of the ETR buffer when stopping. */
+ w_offset = tmc_etr_get_rwp_offset(tmcdrvdata);
+ if (w_offset >= 0)
+ byte_cntr_data->w_offset = w_offset;
+
+ atomic_set(&byte_cntr_data->irq_cnt, 0);
+ byte_cntr_data->read_active = false;
+ byte_cntr_data->enable = false;
+ /*
+ * Wakeup once to force the read function to read the remaining
+ * data of the ETR buffer.
+ */
+ wake_up(&byte_cntr_data->wq);
+}
+
+void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int etr_num)
+{
+ struct ctcu_byte_cntr *byte_cntr_data;
+ struct device_node *nd = dev->of_node;
+ int byte_cntr_irq, ret, i;
+
+ for (i = 0; i < etr_num; i++) {
+ byte_cntr_data = &drvdata->byte_cntr_data[i];
+ byte_cntr_irq = of_irq_get_byname(nd, byte_cntr_data->irq_name);
+ if (byte_cntr_irq < 0) {
+ dev_err(dev, "Failed to get IRQ from DT for %s\n",
+ byte_cntr_data->irq_name);
+ continue;
+ }
+
+ ret = devm_request_irq(dev, byte_cntr_irq, byte_cntr_handler,
+ IRQF_TRIGGER_RISING | IRQF_SHARED,
+ dev_name(dev), byte_cntr_data);
+ if (ret) {
+ dev_err(dev, "Failed to register IRQ for %s\n",
+ byte_cntr_data->irq_name);
+ continue;
+ }
+
+ byte_cntr_data->byte_cntr_irq = byte_cntr_irq;
+ atomic_set(&byte_cntr_data->irq_cnt, 0);
+ init_waitqueue_head(&byte_cntr_data->wq);
+ }
+}
@@ -46,16 +46,22 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu");
#define CTCU_ATID_REG_BIT(traceid) (traceid % 32)
#define CTCU_ATID_REG_SIZE 0x10
#define CTCU_ETR0_ATID0 0xf8
+#define CTCU_ETR0_IRQCTRL 0x6c
#define CTCU_ETR1_ATID0 0x108
+#define CTCU_ETR1_IRQCTRL 0x70
static const struct ctcu_etr_config sa8775p_etr_cfgs[] = {
{
- .atid_offset = CTCU_ETR0_ATID0,
- .port_num = 0,
+ .atid_offset = CTCU_ETR0_ATID0,
+ .irq_ctrl_offset = CTCU_ETR0_IRQCTRL,
+ .irq_name = "etr0",
+ .port_num = 0,
},
{
- .atid_offset = CTCU_ETR1_ATID0,
- .port_num = 1,
+ .atid_offset = CTCU_ETR1_ATID0,
+ .irq_ctrl_offset = CTCU_ETR1_IRQCTRL,
+ .irq_name = "etr1",
+ .port_num = 1,
},
};
@@ -64,6 +70,69 @@ static const struct ctcu_config sa8775p_cfgs = {
.num_etr_config = ARRAY_SIZE(sa8775p_etr_cfgs),
};
+static ssize_t byte_cntr_val_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ int i, len = 0;
+
+ for (i = 0; i < ETR_MAX_NUM; i++) {
+ if (drvdata->byte_cntr_data[i].irq_ctrl_offset)
+ len += scnprintf(buf + len, PAGE_SIZE - len, "%u ",
+ drvdata->byte_cntr_data[i].thresh_val);
+ }
+
+ len += scnprintf(buf + len, PAGE_SIZE - len, "\n");
+
+ return len;
+}
+
+static ssize_t byte_cntr_val_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ u32 thresh_vals[ETR_MAX_NUM] = { 0 };
+ u32 irq_ctrl_offset;
+ int num, i;
+
+ num = sscanf(buf, "%i %i", &thresh_vals[0], &thresh_vals[1]);
+ if (num <= 0 || num > ETR_MAX_NUM)
+ return -EINVAL;
+
+ /* Threshold 0 disables the interruption. */
+ guard(raw_spinlock_irqsave)(&drvdata->spin_lock);
+ for (i = 0; i < num; i++) {
+ /* A small threshold will result in a large number of interruptions */
+ if (thresh_vals[i] && thresh_vals[i] < 4096)
+ return -EINVAL;
+
+ if (drvdata->byte_cntr_data[i].irq_ctrl_offset) {
+ drvdata->byte_cntr_data[i].thresh_val = thresh_vals[i];
+ irq_ctrl_offset = drvdata->byte_cntr_data[i].irq_ctrl_offset;
+ CS_UNLOCK(drvdata->base);
+ writel_relaxed(thresh_vals[i], drvdata->base + irq_ctrl_offset);
+ CS_LOCK(drvdata->base);
+ }
+ }
+
+ return size;
+}
+static DEVICE_ATTR_RW(byte_cntr_val);
+
+static struct attribute *ctcu_attrs[] = {
+ &dev_attr_byte_cntr_val.attr,
+ NULL,
+};
+
+static struct attribute_group ctcu_attr_grp = {
+ .attrs = ctcu_attrs,
+};
+
+static const struct attribute_group *ctcu_attr_grps[] = {
+ &ctcu_attr_grp,
+ NULL,
+};
+
static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset,
u8 bit, bool enable)
{
@@ -122,7 +191,7 @@ static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8 traceid, in
* Searching the sink device from helper's view in case there are multiple helper devices
* connected to the sink device.
*/
-static int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper)
+int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper)
{
struct coresight_platform_data *pdata = helper->pdata;
int i;
@@ -160,6 +229,8 @@ static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, void *
{
struct coresight_path *path = (struct coresight_path *)data;
+ ctcu_byte_cntr_start(csdev, path);
+
return ctcu_set_etr_traceid(csdev, path, true);
}
@@ -167,6 +238,8 @@ static int ctcu_disable(struct coresight_device *csdev, void *data)
{
struct coresight_path *path = (struct coresight_path *)data;
+ ctcu_byte_cntr_stop(csdev, path);
+
return ctcu_set_etr_traceid(csdev, path, false);
}
@@ -217,7 +290,11 @@ static int ctcu_probe(struct platform_device *pdev)
for (i = 0; i < cfgs->num_etr_config; i++) {
etr_cfg = &cfgs->etr_cfgs[i];
drvdata->atid_offset[i] = etr_cfg->atid_offset;
+ drvdata->byte_cntr_data[i].irq_name = etr_cfg->irq_name;
+ drvdata->byte_cntr_data[i].irq_ctrl_offset =
+ etr_cfg->irq_ctrl_offset;
}
+ ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config);
}
}
@@ -229,6 +306,7 @@ static int ctcu_probe(struct platform_device *pdev)
desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU;
desc.pdata = pdata;
desc.dev = dev;
+ desc.groups = ctcu_attr_grps;
desc.ops = &ctcu_ops;
desc.access = CSDEV_ACCESS_IOMEM(base);
@@ -5,6 +5,7 @@
#ifndef _CORESIGHT_CTCU_H
#define _CORESIGHT_CTCU_H
+
#include "coresight-trace-id.h"
/* Maximum number of supported ETR devices for a single CTCU. */
@@ -13,10 +14,14 @@
/**
* struct ctcu_etr_config
* @atid_offset: offset to the ATID0 Register.
- * @port_num: in-port number of CTCU device that connected to ETR.
+ * @irq_ctrl_offset: offset to the BYTECNTRVAL register.
+ * @irq_name: IRQ name in dt node.
+ * @port_num: in-port number of the CTCU device that connected to ETR.
*/
struct ctcu_etr_config {
const u32 atid_offset;
+ const u32 irq_ctrl_offset;
+ const char *irq_name;
const u32 port_num;
};
@@ -25,15 +30,57 @@ struct ctcu_config {
int num_etr_config;
};
+/**
+ * struct ctcu_byte_cntr
+ * @enable: indicates that byte_cntr function is enabled or not.
+ * @read_active: indicates that byte-cntr node is opened or not.
+ * @thresh_val: threshold to trigger a interruption.
+ * @total_size total size of transferred data.
+ * @byte_cntr_irq: IRQ number.
+ * @irq_cnt: IRQ count.
+ * @wq: workqueue of reading ETR data.
+ * @read_work: work of reading ETR data.
+ * @spin_lock: spinlock of byte cntr data.
+ * @r_offset: offset of the pointer where reading begins.
+ * @w_offset: offset of the write pointer in the ETR buffer when
+ * the byte cntr is stopped.
+ * @irq_ctrl_offset: offset to the BYTECNTVAL Register.
+ * @irq_name: IRQ name in DT.
+ */
+struct ctcu_byte_cntr {
+ bool enable;
+ bool read_active;
+ u32 thresh_val;
+ u64 total_size;
+ int byte_cntr_irq;
+ atomic_t irq_cnt;
+ wait_queue_head_t wq;
+ struct work_struct read_work;
+ raw_spinlock_t spin_lock;
+ long r_offset;
+ long w_offset;
+ u32 irq_ctrl_offset;
+ const char *irq_name;
+};
+
struct ctcu_drvdata {
void __iomem *base;
struct clk *apb_clk;
struct device *dev;
struct coresight_device *csdev;
+ struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM];
raw_spinlock_t spin_lock;
u32 atid_offset[ETR_MAX_NUM];
/* refcnt for each traceid of each sink */
u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP];
};
+/* Generic functions */
+int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper);
+
+/* Byte-cntr functions */
+void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path);
+void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path);
+void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int port_num);
+
#endif
@@ -271,6 +271,7 @@ struct tmc_drvdata {
struct etr_buf *perf_buf;
struct tmc_resrv_buf resrv_buf;
struct tmc_resrv_buf crash_mdata;
+ struct ctcu_byte_cntr *byte_cntr_data;
};
struct etr_buf_operations {
The byte-cntr function provided by the CTCU device is used to transfer data from the ETR buffer to the userspace. An interrupt is triggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions and the read function will read the data from the ETR buffer if the IRQ count is greater than 0. Each successful read process will decrement the IRQ count by 1. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> --- drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-ctcu-byte-cntr.c | 119 ++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 88 ++++++++++++- drivers/hwtracing/coresight/coresight-ctcu.h | 49 +++++++- drivers/hwtracing/coresight/coresight-tmc.h | 1 + 5 files changed, 252 insertions(+), 7 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c