| Message ID | 20250410090251.1103979-5-primoz.fiser@norik.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Update PHYTEC i.MX93 DTS | expand |
On Thu, Apr 10, 2025 at 11:02:42AM +0200, Primoz Fiser wrote: > Improve eMMC on phyCORE-i.MX93 SOM by adding 100MHz and 200MHz pinctrl > modes. This enables to use eMMC at enhanced data rates (e.g. HS400). > > While at it, apply a workaround for the i.MX93 chip errata ERR052021. > > Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> > --- > .../boot/dts/freescale/imx93-phycore-som.dtsi | 57 +++++++++++++++---- > 1 file changed, 47 insertions(+), 10 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi > index 82f680d891c2..3d84eed33074 100644 > --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi > @@ -166,8 +166,10 @@ eeprom@50 { > > /* eMMC */ > &usdhc1 { > - pinctrl-names = "default"; > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > bus-width = <8>; > non-removable; > status = "okay"; > @@ -213,18 +215,53 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e > >; > }; > > + /* need to config the SION for data and cmd pad, refer to ERR052021 */ > pinctrl_usdhc1: usdhc1grp { > fsl,pins = < > MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e > - MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 > - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e > - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 > - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e > - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 > - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 > - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 > - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 > - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 > + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386 > + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e > + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386 > + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e > + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001386 > + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386 > + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386 > + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386 > + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386 > + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e > + >; > + }; > + > + /* need to config the SION for data and cmd pad, refer to ERR052021 */ > + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { > + fsl,pins = < > + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be > + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e > + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e any reason why DATA0 is difference with other one? > + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e > + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be > + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e > + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e > + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e > + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e > + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e > + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e > + >; > + }; > + > + /* need to config the SION for data and cmd pad, refer to ERR052021 */ > + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { > + fsl,pins = < > + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be > + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e > + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e any reason why DATA0/DATA1 is difference with other one Frank > + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be > + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be > + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be > + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be > + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be > + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be > + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be > MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e > >; > }; > -- > 2.34.1 >
Hi Frank, On 10. 04. 25 16:56, Frank Li wrote: > On Thu, Apr 10, 2025 at 11:02:42AM +0200, Primoz Fiser wrote: >> Improve eMMC on phyCORE-i.MX93 SOM by adding 100MHz and 200MHz pinctrl >> modes. This enables to use eMMC at enhanced data rates (e.g. HS400). >> >> While at it, apply a workaround for the i.MX93 chip errata ERR052021. >> >> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> >> --- >> .../boot/dts/freescale/imx93-phycore-som.dtsi | 57 +++++++++++++++---- >> 1 file changed, 47 insertions(+), 10 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi >> index 82f680d891c2..3d84eed33074 100644 >> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi >> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi >> @@ -166,8 +166,10 @@ eeprom@50 { >> >> /* eMMC */ >> &usdhc1 { >> - pinctrl-names = "default"; >> + pinctrl-names = "default", "state_100mhz", "state_200mhz"; >> pinctrl-0 = <&pinctrl_usdhc1>; >> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; >> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; >> bus-width = <8>; >> non-removable; >> status = "okay"; >> @@ -213,18 +215,53 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e >> >; >> }; >> >> + /* need to config the SION for data and cmd pad, refer to ERR052021 */ >> pinctrl_usdhc1: usdhc1grp { >> fsl,pins = < >> MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e >> - MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 >> - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e >> - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 >> - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e >> - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 >> - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 >> - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 >> - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 >> - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 >> + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386 >> + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e >> + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386 >> + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e >> + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001386 >> + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386 >> + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386 >> + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386 >> + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386 >> + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e >> + >; >> + }; >> + >> + /* need to config the SION for data and cmd pad, refer to ERR052021 */ >> + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { >> + fsl,pins = < >> + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be >> + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e >> + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e > > any reason why DATA0 is difference with other one? > >> + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e >> + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be >> + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e >> + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e >> + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e >> + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e >> + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e >> + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e >> + >; >> + }; >> + >> + /* need to config the SION for data and cmd pad, refer to ERR052021 */ >> + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { >> + fsl,pins = < >> + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be >> + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e >> + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e > > any reason why DATA0/DATA1 is difference with other one Bus signal integrity envelope was measured and drive-strengths adjusted accordingly by the PHYTEC hardware department to conform to the specs. Values were thus determined empirically to adjust for differences in signal impedance due to PCB layout. BR, Primoz > > Frank >> + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be >> + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be >> + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be >> + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be >> + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be >> + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be >> + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be >> MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e >> >; >> }; >> -- >> 2.34.1 >>
On Fri, Apr 11, 2025 at 08:29:05AM +0200, Primoz Fiser wrote: > Hi Frank, > > On 10. 04. 25 16:56, Frank Li wrote: > > On Thu, Apr 10, 2025 at 11:02:42AM +0200, Primoz Fiser wrote: > >> Improve eMMC on phyCORE-i.MX93 SOM by adding 100MHz and 200MHz pinctrl > >> modes. This enables to use eMMC at enhanced data rates (e.g. HS400). > >> > >> While at it, apply a workaround for the i.MX93 chip errata ERR052021. > >> > >> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> > >> --- > >> .../boot/dts/freescale/imx93-phycore-som.dtsi | 57 +++++++++++++++---- > >> 1 file changed, 47 insertions(+), 10 deletions(-) > >> > >> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi > >> index 82f680d891c2..3d84eed33074 100644 > >> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi > >> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi > >> @@ -166,8 +166,10 @@ eeprom@50 { > >> > >> /* eMMC */ > >> &usdhc1 { > >> - pinctrl-names = "default"; > >> + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > >> pinctrl-0 = <&pinctrl_usdhc1>; > >> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > >> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > >> bus-width = <8>; > >> non-removable; > >> status = "okay"; > >> @@ -213,18 +215,53 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e > >> >; > >> }; > >> > >> + /* need to config the SION for data and cmd pad, refer to ERR052021 */ > >> pinctrl_usdhc1: usdhc1grp { > >> fsl,pins = < > >> MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e > >> - MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 > >> - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e > >> - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 > >> - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e > >> - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 > >> - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 > >> - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 > >> - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 > >> - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 > >> + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386 > >> + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e > >> + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386 > >> + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e > >> + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001386 > >> + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386 > >> + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386 > >> + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386 > >> + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386 > >> + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e > >> + >; > >> + }; > >> + > >> + /* need to config the SION for data and cmd pad, refer to ERR052021 */ > >> + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { > >> + fsl,pins = < > >> + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be > >> + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e > >> + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e > > > > any reason why DATA0 is difference with other one? > > > >> + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e > >> + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be > >> + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e > >> + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e > >> + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e > >> + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e > >> + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e > >> + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e > >> + >; > >> + }; > >> + > >> + /* need to config the SION for data and cmd pad, refer to ERR052021 */ > >> + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { > >> + fsl,pins = < > >> + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be > >> + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e > >> + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e > > > > any reason why DATA0/DATA1 is difference with other one > > Bus signal integrity envelope was measured and drive-strengths adjusted > accordingly by the PHYTEC hardware department to conform to the specs. > > Values were thus determined empirically to adjust for differences in > signal impedance due to PCB layout. Okay thanks, I just to make sure it is not typo. Frank > > BR, > Primoz > > > > > Frank > >> + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be > >> + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be > >> + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be > >> + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be > >> + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be > >> + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be > >> + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be > >> MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e > >> >; > >> }; > >> -- > >> 2.34.1 > >> > > -- > Primoz Fiser > phone: +386-41-390-545 > email: primoz.fiser@norik.com > -- > Norik systems d.o.o. > Your embedded software partner > Slovenia, EU > phone: +386-41-540-545 > email: info@norik.com
diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 82f680d891c2..3d84eed33074 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -166,8 +166,10 @@ eeprom@50 { /* eMMC */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; status = "okay"; @@ -213,18 +215,53 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e - MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001386 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e >; };
Improve eMMC on phyCORE-i.MX93 SOM by adding 100MHz and 200MHz pinctrl modes. This enables to use eMMC at enhanced data rates (e.g. HS400). While at it, apply a workaround for the i.MX93 chip errata ERR052021. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> --- .../boot/dts/freescale/imx93-phycore-som.dtsi | 57 +++++++++++++++---- 1 file changed, 47 insertions(+), 10 deletions(-)