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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Piotr Oniszczuk Subject: [PATCH 5/6] arm64: dts: allwinner: A523: Add thermal sensors and zones Date: Fri, 11 Apr 2025 08:38:25 +0800 Message-ID: <20250411003827.782544-6-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250411003827.782544-1-iuncuim@gmail.com> References: <20250411003827.782544-1-iuncuim@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250410_174044_936284_5C16C4E3 X-CRM114-Status: GOOD ( 13.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mikhail Kalashnikov The A523 processor has two temperature controllers, THS0 and THS1. THS0 has only one temperature sensor, which is located in the DRAM. THS1 does have 3 sensors: ths1_0 - "big" cores ths1_1 - "little" cores ths1_2 - gpu Add the thermal sensor configuration and the thermal zones Signed-off-by: Mikhail Kalashnikov --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index d626612bb..4f36032b2 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -22,6 +23,7 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0x000>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu1: cpu@100 { @@ -29,6 +31,7 @@ cpu1: cpu@100 { device_type = "cpu"; reg = <0x100>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -36,6 +39,7 @@ cpu2: cpu@200 { device_type = "cpu"; reg = <0x200>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -43,6 +47,7 @@ cpu3: cpu@300 { device_type = "cpu"; reg = <0x300>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu4: cpu@400 { @@ -50,6 +55,7 @@ cpu4: cpu@400 { device_type = "cpu"; reg = <0x400>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu5: cpu@500 { @@ -57,6 +63,7 @@ cpu5: cpu@500 { device_type = "cpu"; reg = <0x500>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu6: cpu@600 { @@ -64,6 +71,7 @@ cpu6: cpu@600 { device_type = "cpu"; reg = <0x600>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu7: cpu@700 { @@ -71,6 +79,7 @@ cpu7: cpu@700 { device_type = "cpu"; reg = <0x700>; enable-method = "psci"; + #cooling-cells = <2>; }; }; @@ -171,11 +180,39 @@ ccu: clock-controller@2001000 { #reset-cells = <1>; }; + ths1: thermal-sensor@2009400 { + compatible = "allwinner,sun55i-a523-ths1"; + reg = <0x02009400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>; + clock-names = "bus", "gpadc"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + + ths0: thermal-sensor@200a000 { + compatible = "allwinner,sun55i-a523-ths0"; + reg = <0x0200a000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC0>; + clock-names = "bus", "gpadc"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + sid: efuse@3006000 { compatible = "allwinner,sun50i-a523-sid", "allwinner,sun50i-a64-sid"; reg = <0x03006000 0x1000>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@38 { + reg = <0x38 0x14>; + }; }; mmc0: mmc@4020000 { @@ -602,4 +639,105 @@ rtc: rtc@7090000 { #clock-cells = <1>; }; }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <500>; + polling-delay = <1000>; + thermal-sensors = <&ths1 1>; + sustainable-power = <1200>; + + trips { + cpu0_threshold: cpu-trip-0 { + temperature = <70000>; + type = "passive"; + hysteresis = <0>; + }; + cpu0_target: cpu-trip-1 { + temperature = <90000>; + type = "passive"; + hysteresis = <0>; + }; + cpu0_critical: cpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4_thermal: cpu4-thermal { + polling-delay-passive = <500>; + polling-delay = <1000>; + thermal-sensors = <&ths1 0>; + sustainable-power = <1600>; + + trips { + cpu4_threshold: cpu-trip-0 { + temperature = <70000>; + type = "passive"; + hysteresis = <0>; + }; + cpu4_target: cpu-trip-1 { + temperature = <90000>; + type = "passive"; + hysteresis = <0>; + }; + cpu4_critical: cpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_target>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <500>; + polling-delay = <1000>; + thermal-sensors = <&ths1 2>; + sustainable-power = <2400>; + + trips { + gpu_temp_critical: gpu-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths0>; + + trips { + ddr_temp_critical: ddr-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + }; };