@@ -7,6 +7,7 @@
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>
#include "k3-serdes.h"
@@ -126,6 +127,11 @@ audio_refclk1: clock@82e4 {
assigned-clock-parents = <&k3_clks 157 63>;
#clock-cells = <0>;
};
+
+ acspcie0_proxy_ctrl: clock-controller@1a090 {
+ compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
+ reg = <0x1a090 0x4>;
+ };
};
main_ehrpwm0: pwm@3000000 {
@@ -1093,8 +1099,8 @@ pcie1_rc: pcie@2910000 {
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 333 0>;
- clock-names = "fck";
+ clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
@@ -1105,6 +1111,7 @@ pcie1_rc: pcie@2910000 {
ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
<0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>;
status = "disabled";
};
The PCIe reference clock required by the PCIe Endpoints connected to the PCIe connector corresponding to the PCIe1 instance of PCIe on J784S4-EVM and J742S2-EVM is driven by the ACSPCIE module. Add the device-tree support for enabling the same. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- Hello, This patch is based on linux-next tagged next-20250411. The v2 patch is at: https://lore.kernel.org/r/20241209085157.1203168-1-s-vadapalli@ti.com/ No changes since v2. The dtbs_check warnings are no longer seen with next-20250411 and no changes were required to the patch itself to fix the warnings. Hence the patch has been marked with a RESEND tag. Regards, Siddharth. .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)