| Message ID | 20250416010141.1785841-7-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [V2,01/10] arm64: dts: imx8mm-beacon: Fix RTC capacitive load | expand |
On Tue, Apr 15, 2025 at 08:01:33PM -0500, Adam Ford wrote: > The Ethernet PHY setup currently assumes that the bootloader will take the > PHY out of reset, but this behavior is not guaranteed across all > bootloaders. Add the reset GPIO to ensure the kernel can properly control > the PHY reset line. > > Also configure the PHY IRQ GPIO to enable interrupt-driven link status > reporting, instead of relying on polling. > > This ensures more reliable Ethernet initialization and improves PHY event > handling. > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- Reviewed-by: Frank Li <Frank.Li@nxp.com> > V2: Update commit message. No active changes. > > arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi > index bb11590473a4..b3692b367a42 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi > @@ -88,6 +88,9 @@ mdio { > ethphy0: ethernet-phy@0 { > compatible = "ethernet-phy-ieee802.3-c22"; > reg = <0>; > + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; > + interrupt-parent = <&gpio1>; > + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; > }; > }; > }; > @@ -326,6 +329,7 @@ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f > MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 > MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 > MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f > + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 > MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 > >; > }; > -- > 2.48.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index bb11590473a4..b3692b367a42 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -88,6 +88,9 @@ mdio { ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -326,6 +329,7 @@ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 >; };
The Ethernet PHY setup currently assumes that the bootloader will take the PHY out of reset, but this behavior is not guaranteed across all bootloaders. Add the reset GPIO to ensure the kernel can properly control the PHY reset line. Also configure the PHY IRQ GPIO to enable interrupt-driven link status reporting, instead of relying on polling. This ensures more reliable Ethernet initialization and improves PHY event handling. Signed-off-by: Adam Ford <aford173@gmail.com> --- V2: Update commit message. No active changes. arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+)