From patchwork Thu Apr 17 12:04:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 14055470 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D74B3C369B2 for ; Thu, 17 Apr 2025 12:34:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bNb2Dq3nRm0e9cZYsstRIDuGhQAYPxcy2C0B5OtXSxA=; b=X0UPeN9YiT2t3Teuud3Z8GQ6aL oTbWkO0UJqfcZVSbx5qywdKNOiMER7WpGCb6dSsvGZ8g5PUjnu9JyeS6nleQpxFN6V6uycLtnGl+D TB7Ph/NDKHhx9gEqcMjuegObEqaRd8z6euEAi40EIPEzXdIm3FXGG+86XoFHzMRbyNWb/oZ+G8K+F Z1TfIhYBE5EKwb9WNNlMOX32DCaGxyyuhucXcAtoaFAHKmPGhdIKuvkZbXLNO/nN3kRCqf58GI1mc OoiWUgJJwwiJgJKszkfKNeuDaGdue41CLR1BhznEefvSh587bPq0jF9qt+NMuwH821e/IEZX3Jzn+ L6zVm2eA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5ORV-0000000CyOv-2NLZ; Thu, 17 Apr 2025 12:34:09 +0000 Received: from lelvem-ot01.ext.ti.com ([198.47.23.234]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5Nyx-0000000CrnF-0cwW for linux-arm-kernel@lists.infradead.org; Thu, 17 Apr 2025 12:04:40 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53HC4Zng3094834 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 07:04:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744891475; bh=bNb2Dq3nRm0e9cZYsstRIDuGhQAYPxcy2C0B5OtXSxA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=haR2lQSFJFH6A+nCi48gmimFDOkgu4Gk9bRGANzDO8ngRqPZt87jtFL1swhmWEOjx io3FAjcSpr6XzyBNhyXSUgnHU8nDHUoPS3+7nPvKU37LvzgH4WjbXF2a++uQ8gGbuz V7E2uLRSw5i4NM7IGLK+BGrtE9tcIVZxYPJYgtxE= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53HC4Z6F083673 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 07:04:35 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 07:04:35 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 07:04:35 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HC47VP004789; Thu, 17 Apr 2025 07:04:32 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1 Date: Thu, 17 Apr 2025 17:34:07 +0530 Message-ID: <20250417120407.2646929-8-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417120407.2646929-1-s-vadapalli@ti.com> References: <20250417120407.2646929-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250417_050439_274266_BEA70C2A X-CRM114-Status: GOOD ( 10.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PCIe0 and PCIe1 instances of PCIe in J742S2 and J784S4 SoCs support: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli --- .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 1944616ab357..0cbf0fba9112 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -1055,7 +1055,7 @@ pcie0_rc: pcie@2900000 { reg = <0x00 0x02900000 0x00 0x1000>, <0x00 0x02907000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; + <0x40 0x00000000 0x00 0x00001000>; reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; @@ -1073,8 +1073,9 @@ pcie0_rc: pcie@2900000 { device-id = <0xb012>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */ + <0x43000000 0x40 0x08101000 0x40 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; @@ -1084,7 +1085,7 @@ pcie1_rc: pcie@2910000 { reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; @@ -1102,8 +1103,9 @@ pcie1_rc: pcie@2910000 { device-id = <0xb012>; msi-map = <0x0 &gic_its 0x10000 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */ + <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; };