Message ID | 20250417123246.2733923-4-s-vadapalli@ti.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | J722S: Disable WIZ0 and WIZ1 in SoC file | expand |
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index beda9e40e931..562dfbdf449d 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -52,8 +52,6 @@ serdes0: serdes@f000000 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; - - status = "disabled"; /* Needs lane config */ }; }; @@ -92,8 +90,6 @@ serdes1: serdes@f010000 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; - - status = "disabled"; /* Needs lane config */ }; };