Message ID | 20250417123246.2733923-5-s-vadapalli@ti.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | J722S: Disable WIZ0 and WIZ1 in SoC file | expand |
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 0bf2e1821662..34b9d190800e 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -848,7 +848,6 @@ &serdes_wiz0 { }; &serdes0 { - status = "okay"; serdes0_usb_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; @@ -863,7 +862,6 @@ &serdes_wiz1 { }; &serdes1 { - status = "okay"; serdes1_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <1>;