From patchwork Sun Dec 14 23:49:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 5489531 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 63AF09F1CD for ; Sun, 14 Dec 2014 23:51:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5347020937 for ; Sun, 14 Dec 2014 23:51:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4AD64209FF for ; Sun, 14 Dec 2014 23:51:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y0IvF-0004gG-6v; Sun, 14 Dec 2014 23:49:57 +0000 Received: from galahad.ideasonboard.com ([185.26.127.97]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y0IvA-0004b7-Ru for linux-arm-kernel@lists.infradead.org; Sun, 14 Dec 2014 23:49:53 +0000 Received: from avalon.localnet (dsl-hkibrasgw3-50ddcc-40.dhcp.inet.fi [80.221.204.40]) by galahad.ideasonboard.com (Postfix) with ESMTPSA id 71A1D20B64; Mon, 15 Dec 2014 00:46:16 +0100 (CET) From: Laurent Pinchart To: linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 0/4] Generic IOMMU page table framework Date: Mon, 15 Dec 2014 01:49:30 +0200 Message-ID: <2133922.nksBEtjI2q@avalon> User-Agent: KMail/4.14.3 (Linux/3.16.5-gentoo; KDE/4.14.3; x86_64; ; ) In-Reply-To: <1417089078-22900-1-git-send-email-will.deacon@arm.com> References: <1417089078-22900-1-git-send-email-will.deacon@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141214_154953_221630_DCBB8C6C X-CRM114-Status: GOOD ( 26.42 ) X-Spam-Score: -0.0 (/) Cc: lauraa@codeaurora.org, Robin.Murphy@arm.com, joro@8bytes.org, Will Deacon , iommu@lists.linux-foundation.org, Varun.Sethi@freescale.com, prem.mallappa@broadcom.com, mitchelh@codeaurora.org, m.szyprowski@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Will, On Thursday 27 November 2014 11:51:14 Will Deacon wrote: > Hi all, > > This series introduces a generic IOMMU page table allocation framework, > implements support for ARM long-descriptors and then ports the arm-smmu > driver over to the new code. > > There are a few reasons for doing this: > > - Page table code is hard, and I don't enjoy shopping > > - A number of IOMMUs actually use the same table format, but currently > duplicate the code > > - It provides a CPU (and architecture) independent allocator, which > may be useful for some systems where the CPU is using a different > table format for its own mappings > > As illustrated in the final patch, an IOMMU driver interacts with the > allocator by passing in a configuration structure describing the > input and output address ranges, the supported pages sizes and a set of > ops for performing various TLB invalidation and PTE flushing routines. > > The LPAE code implements support for 4k/2M/1G, 16k/32M and 64k/512M > mappings, but I decided not to implement the contiguous bit in the > interest of trying to keep the code semi-readable. This could always be > added later, if needed. > > I also included some self-tests for the LPAE implementation. Ideally > we'd merge these, but I'm also happy to drop them if there are > objections. > > Tested with the self-tests, but also VFIO + MMU-500 at stage-1 and > stage-2. Patches taken against my iommu/devel branch (queued by Joerg > for 3.19). > > All feedback welcome. I've successfully tested the patch set with the Renesas IPMMU-VMSA driver with the following extension to the allocator. Tested-by: Laurent Pinchart From 4bebb7f3a5a48541d4c89ce7c61e6ff66686c3a9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 14 Dec 2014 23:34:50 +0200 Subject: [PATCH] iommu: io-pgtable-arm: Add Non-Secure quirk The quirk causes the Non-Secure bit to be set in all page table entries. Signed-off-by: Laurent Pinchart --- drivers/iommu/io-pgtable-arm.c | 7 +++++++ drivers/iommu/io-pgtable.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index 669e322a83a4..b6910e142734 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -80,11 +80,13 @@ #define ARM_LPAE_PTE_TYPE_TABLE 3 #define ARM_LPAE_PTE_TYPE_PAGE 3 +#define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63) #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53) #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10) #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8) #define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8) #define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8) +#define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5) #define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0) #define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2) @@ -201,6 +203,9 @@ static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data, if (iopte_leaf(*ptep, lvl)) return -EEXIST; + if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_NON_SECURE) + pte |= ARM_LPAE_PTE_NS; + if (lvl == ARM_LPAE_MAX_LEVELS - 1) pte |= ARM_LPAE_PTE_TYPE_PAGE; else @@ -244,6 +249,8 @@ static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova, data->iop.cfg.tlb->flush_pgtable(cptep, 1UL << data->pg_shift, cookie); pte = __pa(cptep) | ARM_LPAE_PTE_TYPE_TABLE; + if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_NON_SECURE) + pte |= ARM_LPAE_PTE_NSTABLE; *ptep = pte; data->iop.cfg.tlb->flush_pgtable(ptep, sizeof(*ptep), cookie); } else { diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h index c1cff3d045db..a41a15d30596 100644 --- a/drivers/iommu/io-pgtable.h +++ b/drivers/iommu/io-pgtable.h @@ -24,6 +24,9 @@ struct iommu_gather_ops { void (*flush_pgtable)(void *ptr, size_t size, void *cookie); }; +/* Set the Non-Secure bit in the PTEs */ +#define IO_PGTABLE_QUIRK_NON_SECURE (1 << 0) + struct io_pgtable_cfg { int quirks; /* IO_PGTABLE_QUIRK_* */ unsigned long pgsize_bitmap;