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Mon, 21 Oct 2024 17:20:14 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 11/11] iommu/arm-smmu-v3: Add IOMMU_VIOMMU_TYPE_ARM_SMMUV3 support Date: Mon, 21 Oct 2024 17:19:33 -0700 Message-ID: <2180fdf423d0f2fcc5c031687690100b12c2ba51.1729553811.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000149:EE_|DM4PR12MB6373:EE_ X-MS-Office365-Filtering-Correlation-Id: f825288c-75dd-409e-dd07-08dcf22f5759 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: +xWBkhnQKCM8cYW8/birDoG0OTXP1N8Kg3NN8kWTm9veASJoBc4T4pJL1QrLGjaTr2AFrLp3PcGf9096jZ6Zc0+gTgt7xJldQQzvWaqYW3EEOZ8tVrHB+ErOKzUPHQEcq0mrQkVJjia5EHPtYOdfSrtnYJWP1Q4uEyQCl31eM81QtRD0L1C+rNb3hZ4foYEs6EjPakMwzg2me3OGBfg3sNsFMaeMMvkuI+lBeXB3Zh1j/eTSSkMcpJoPSaXjqwpp2VbC+7ifXxeat4QcxCqds5m29LA/1VdBirw/r2dfBA0JOeombE20J/dY0owgGLvIojph+ys3GFk6nbzHlLgrCWNvMY+JT1YpL/JKhQ9d+7rJFzXAI4+Px95NSlniz8DA3IvTXEza7xLPcxC4C6wpj+qPW9gjNrs6wQoJBwe4AWSWOf3QOfFWWFlQ3irm8O0rv9JwxLkiHn6Nyt2i7gpb7K1PcBGFTsQ7N5nYxcFSEibEEXq2xMS7buEiH5dkJmULuZKuxkJx+Mf06rJQuRTHG8fFH64A8QBiuWenHjqLKIO1UwLLbaHB7i2/DKj+LlBcfBUYcRsJcxcDZ/qHGTP+Aex+BOB8muLABy+4C4JtDW7v6Uf1/zc+hVRKJpOd2pAWfgSfyrsh4tjewg0dO9zU4J3TYye9kpK2jynJwbf4HH9P2idCrdPnOvUgsV99YQ64o3LQFSTKpYT18i4aM+PJHLiejaaCMmBur7sOiBNhMls/idjRSlZOO8ArL5huf+kMmwHmFmlyd82Oih+CDxp5TpQUgD/ZUHft8VE6smZuFcC7m9rLZg4xtOiBEeLWOyiVCcNPNX7xst1xGmM7wfjC2aI1F3tWEpEL0MdKH1ok13bi8Ov44ELH9H2apD5XONdpYpHdSNK87f7ddp1qoZryvpe9kQVEteeTf741uuxb+t3OvPaPachFwdtyjHmhWz/1D1o84oQlulIwoIzVCsgZlnwtxzuwhv9VIfgws5Z1YFM4C/+mZgXp1WyYMYkMpj4CJ+HMeeXChSS9RjAZ+h/GUv6WFcf5RUuwhjj7sBlXCifIp/AIT4D5v2GUMyCJN4z6KU40ps4K68+n6v4KrafUwdkNNn/eCJnWdR6E+I94faH3z28OlelbhuPW70yA0iFFIqSlKa5JN19NGxnwsH2U33dRzXp69Q6pJVK59297BUUyJXyFpiVZuUmWLUiga7/5Lybr5HqEp6JJ5HqnJo/fklQx2ztrl6AQA/m4/oZyvfEP9i0C40xivGmfgO7IfoOC+R4swhbvkSg3JEPqVUAIgHvOXWAYEfcrAaVBxJBW6jcq0ss4/DPKMMdBpPXpE/y70mGngqAkR7Qe/ewHvju/ypO1RNueAPmJunn6KaXMjWkHD4s+uTEELyol0xleMcKD1qLLxLSX2rIYbTY9qGbTSQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2024 00:20:32.1253 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f825288c-75dd-409e-dd07-08dcf22f5759 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000149.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6373 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241021_172042_957092_E017CA65 X-CRM114-Status: GOOD ( 22.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a new driver-type for ARM SMMUv3 to enum iommu_viommu_type. Implement an arm_vsmmu_alloc() with its viommu op arm_vsmmu_domain_alloc_nested(), to replace arm_smmu_domain_alloc_nesting(). As an initial step, copy the VMID from s2_parent. A later cleanup series is required to move the VMID allocation out of the stage-2 domain allocation routine to this. After that, replace nested_domain->s2_parent with nested_domain->vsmmu. Note that the validatting conditions for a nested_domain allocation are moved from arm_vsmmu_domain_alloc_nested to arm_vsmmu_alloc, since there is no point in creating a vIOMMU (vsmmu) from the beginning if it would not support a nested_domain. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 26 +++--- include/uapi/linux/iommufd.h | 2 + .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 79 ++++++++++++------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 +-- 4 files changed, 70 insertions(+), 46 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 956c12637866..5a025d310dbe 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -835,7 +836,7 @@ struct arm_smmu_domain { struct arm_smmu_nested_domain { struct iommu_domain domain; - struct arm_smmu_domain *s2_parent; + struct arm_vsmmu *vsmmu; __le64 ste[2]; }; @@ -1005,21 +1006,22 @@ tegra241_cmdqv_probe(struct arm_smmu_device *smmu) } #endif /* CONFIG_TEGRA241_CMDQV */ +struct arm_vsmmu { + struct iommufd_viommu core; + struct arm_smmu_device *smmu; + struct arm_smmu_domain *s2_parent; + u16 vmid; +}; + #if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD) void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type); -struct iommu_domain * -arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, - struct iommu_domain *parent, - const struct iommu_user_data *user_data); +struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, + struct iommu_domain *parent, + struct iommufd_ctx *ictx, + unsigned int viommu_type); #else #define arm_smmu_hw_info NULL -static inline struct iommu_domain * -arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, - struct iommu_domain *parent, - const struct iommu_user_data *user_data) -{ - return ERR_PTR(-EOPNOTSUPP); -} +#define arm_vsmmu_alloc NULL #endif /* CONFIG_ARM_SMMU_V3_IOMMUFD */ #endif /* _ARM_SMMU_V3_H */ diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index f835ccf4a494..09c1b4ba46d8 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -859,9 +859,11 @@ struct iommu_fault_alloc { /** * enum iommu_viommu_type - Virtual IOMMU Type * @IOMMU_VIOMMU_TYPE_DEFAULT: Reserved for future use + * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type */ enum iommu_viommu_type { IOMMU_VIOMMU_TYPE_DEFAULT = 0, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1, }; /** diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 44e1b9bef850..70ad857a57b8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -34,7 +34,8 @@ static void arm_smmu_make_nested_cd_table_ste( struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_nested_domain *nested_domain, bool ats_enabled) { - arm_smmu_make_s2_domain_ste(target, master, nested_domain->s2_parent, + arm_smmu_make_s2_domain_ste(target, master, + nested_domain->vsmmu->s2_parent, ats_enabled); target->data[0] = cpu_to_le64(STRTAB_STE_0_V | @@ -75,7 +76,8 @@ static void arm_smmu_make_nested_domain_ste( break; case STRTAB_STE_0_CFG_BYPASS: arm_smmu_make_s2_domain_ste( - target, master, nested_domain->s2_parent, ats_enabled); + target, master, nested_domain->vsmmu->s2_parent, + ats_enabled); break; case STRTAB_STE_0_CFG_ABORT: default: @@ -100,7 +102,7 @@ static int arm_smmu_attach_dev_nested(struct iommu_domain *domain, struct arm_smmu_ste ste; int ret; - if (nested_domain->s2_parent->smmu != master->smmu) + if (nested_domain->vsmmu->smmu != master->smmu) return -EINVAL; if (arm_smmu_ssids_in_use(&master->cd_table)) return -EBUSY; @@ -151,36 +153,15 @@ static int arm_smmu_validate_vste(struct iommu_hwpt_arm_smmuv3 *arg) return 0; } -struct iommu_domain * -arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, - struct iommu_domain *parent, +static struct iommu_domain * +arm_vsmmu_domain_alloc_nested(struct iommufd_viommu *viommu, const struct iommu_user_data *user_data) { - struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct arm_vsmmu *vsmmu = container_of(viommu, struct arm_vsmmu, core); struct arm_smmu_nested_domain *nested_domain; - struct arm_smmu_domain *smmu_parent; struct iommu_hwpt_arm_smmuv3 arg; int ret; - if (flags || !(master->smmu->features & ARM_SMMU_FEAT_NESTING)) - return ERR_PTR(-EOPNOTSUPP); - - /* - * Must support some way to prevent the VM from bypassing the cache - * because VFIO currently does not do any cache maintenance. - */ - if (!arm_smmu_master_canwbs(master) && - !(master->smmu->features & ARM_SMMU_FEAT_S2FWB)) - return ERR_PTR(-EOPNOTSUPP); - - /* - * The core code checks that parent was created with - * IOMMU_HWPT_ALLOC_NEST_PARENT - */ - smmu_parent = to_smmu_domain(parent); - if (smmu_parent->smmu != master->smmu) - return ERR_PTR(-EINVAL); - ret = iommu_copy_struct_from_user(&arg, user_data, IOMMU_HWPT_DATA_ARM_SMMUV3, ste); if (ret) @@ -196,9 +177,51 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, nested_domain->domain.type = IOMMU_DOMAIN_NESTED; nested_domain->domain.ops = &arm_smmu_nested_ops; - nested_domain->s2_parent = smmu_parent; + nested_domain->vsmmu = vsmmu; nested_domain->ste[0] = arg.ste[0]; nested_domain->ste[1] = arg.ste[1] & ~cpu_to_le64(STRTAB_STE_1_EATS); return &nested_domain->domain; } + + +static const struct iommufd_viommu_ops arm_vsmmu_ops = { + .domain_alloc_nested = arm_vsmmu_domain_alloc_nested, +}; + +struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, + struct iommu_domain *parent, + struct iommufd_ctx *ictx, + unsigned int viommu_type) +{ + struct arm_smmu_device *smmu = + iommu_get_iommu_dev(dev, struct arm_smmu_device, iommu); + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct arm_smmu_domain *s2_parent = to_smmu_domain(parent); + struct arm_vsmmu *vsmmu; + + if (viommu_type != IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + return ERR_PTR(-EOPNOTSUPP); + + if (!(smmu->features & ARM_SMMU_FEAT_NESTING)) + return ERR_PTR(-EOPNOTSUPP); + + /* + * Must support some way to prevent the VM from bypassing the cache + * because VFIO currently does not do any cache maintenance. + */ + if (!arm_smmu_master_canwbs(master) && + !(smmu->features & ARM_SMMU_FEAT_S2FWB)) + return ERR_PTR(-EOPNOTSUPP); + + vsmmu = iommufd_viommu_alloc(ictx, arm_vsmmu, core, &arm_vsmmu_ops); + if (IS_ERR(vsmmu)) + return ERR_CAST(vsmmu); + + vsmmu->smmu = smmu; + vsmmu->s2_parent = s2_parent; + /* FIXME Move VMID allocation from the S2 domain allocation to here */ + vsmmu->vmid = s2_parent->s2_cfg.vmid; + + return &vsmmu->core; +} diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index c7cc98961019..de598d66b5c2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2661,7 +2661,7 @@ to_smmu_domain_devices(struct iommu_domain *domain) domain->type == IOMMU_DOMAIN_SVA) return to_smmu_domain(domain); if (domain->type == IOMMU_DOMAIN_NESTED) - return to_smmu_nested_domain(domain)->s2_parent; + return to_smmu_nested_domain(domain)->vsmmu->s2_parent; return NULL; } @@ -3126,13 +3126,9 @@ arm_smmu_domain_alloc_user(struct device *dev, u32 flags, struct arm_smmu_domain *smmu_domain; int ret; - if (parent) - return arm_smmu_domain_alloc_nesting(dev, flags, parent, - user_data); - if (flags & ~PAGING_FLAGS) return ERR_PTR(-EOPNOTSUPP); - if (user_data) + if (parent || user_data) return ERR_PTR(-EOPNOTSUPP); smmu_domain = arm_smmu_domain_alloc(); @@ -3541,6 +3537,7 @@ static struct iommu_ops arm_smmu_ops = { .dev_disable_feat = arm_smmu_dev_disable_feature, .page_response = arm_smmu_page_response, .def_domain_type = arm_smmu_def_domain_type, + .viommu_alloc = arm_vsmmu_alloc, .user_pasid_table = 1, .pgsize_bitmap = -1UL, /* Restricted during device attach */ .owner = THIS_MODULE,